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CY7C1021B-15VC

P1-P3P4-P6P7-P9P10-P10
1-Mbit (64K x 16) Static RAM
CY7C1021B
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05145 Rev. *C Revised September 28, 2006
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
•High speed
—t
AA
= 12 ns (Commercial & Industrial)
—t
AA
= 15 ns (Automotive)
• CMOS for optimum speed/power
• Low active power
— 770 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II and
44-pin 400-mil-wide SOJ
Functional Description
[1]
The CY7C1021B is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B is available in standard 44-pin TSOP Type II
and 44-pin 400-mil-wide SOJ packages.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
I/O
1
–I/O
8
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
512 X 2048
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O
9
–I/O
16
CE
WE
BLE
BHE
A
8
[+] Feedback
CY7C1021B
Document #: 38-05145 Rev. *C Page 2 of 10
Pin Configurations
Selection Guide
-12 -15
Maximum Access Time (ns) 12 15
Maximum Operating Current (mA) Com’l/Ind’l 140 130
Automotive 130
Maximum CMOS Standby Current (mA) Com’l/Ind’l 10 10
Automotive 15
L Version 0.5 0.5
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ/TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
A
4
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
Pin Definitions
Pin Name SOJ, TSOP–Pin Number I/O Type Description
A
0
–A
15
1–5,18–21, 24–27, 42–44 Input Address Inputs used to select one of the address locations.
I/O
1
–I/O
16
7–10, 13–16, 29–32,
35–38
Input/Output Bidirectional Data I/O lines. Used as input or output lines depending
on operation.
NC 22, 23, 28 No Connect No Connects. Not connected to the die.
WE
17 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
CE
6 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When
HIGH, deselects the chip.
BHE
, BLE 40, 39 Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O
16
–I/O
9,
BLE controls I/O
8
–I/O
1
.
OE
41 Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
V
SS
12, 34 Ground Ground for the device. Should be connected to ground of the
system.
V
CC
11, 33 Power Supply Power Supply inputs to the device.
[+] Feedback
CY7C1021B
Document #: 38-05145 Rev. *C Page 3 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
CC
Relative to GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
......................................–0.5V to V
CC
+0.5V
DC Input Voltage
[2]
...................................–0.5V to V
CC
+0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Ambient
Temperature (T
A
)
[3]
V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
Automotive –40°C to +125°C5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description
Test
Conditions
-12 -15
UnitMin. Max. Min. Max.
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 6.0 2.2 6.0 V
V
IL
Input LOW Voltage
[2]
–0.5 0.8 –0.5 0.8 V
I
IX
Input Leakage Current GND < V
I
< V
CC
Com’l/Ind’l –1 +1 –1 +1 µA
Auto –4 +4 µA
I
OZ
Output Leakage Current GND < V
I
< V
CC
,
Output Disabled
Com’l/Ind’l –1 +1 –1 +1 µA
Auto –4 +4 µA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l/Ind’l 140 130 mA
Auto 130 mA
I
SB1
Automatic CE
Power Down Current —TTL
Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f =
f
MAX
Com’l/Ind’l 40 40 mA
Auto 50 mA
I
SB2
Automatic CE
Power Down Current
—CMOS Inputs
Max. V
CC
, CE > V
CC
–
0.3V, V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l/Ind’l 10 10 mA
Auto 15 mA
L Version 0.5 0.5 mA
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
8pF
C
OUT
Output Capacitance 8 pF
Thermal Resistance
[4]
Parameter Description Test Conditions 44-pin SOJ
44-pin
TSOP-II Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51.
64.32 76.89 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
31.03 14.28 °C/W
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
3. T
A
is the “Instant On” case temperature.
4. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback
P1-P3P4-P6P7-P9P10-P10

CY7C1021B-15VC

Mfr. #:
Buy CY7C1021B-15VC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1M PARALLEL 44SOJ
Lifecycle:
New from this manufacturer.
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