74LVC06A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 14 May 2013 6 of 15
NXP Semiconductors
74LVC06A-Q100
Hex inverter with open-drain outputs
10. Dynamic characteristics
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 7.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
PZL
OFF-state to LOW
propagation delay
nA to nY; see Figure 6
V
CC
= 1.2 V - 9 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 2.8 5.7 0.5 6.7 ns
V
CC
= 2.3 V to 2.7 V 0.5 1.9 3.1 0.5 4.0 ns
V
CC
= 2.7 V 0.5 1.8 3.9 0.5 5.0 ns
V
CC
= 3.0 V to 3.6 V 0.5 1.8 3.7 0.5 5.0 ns
V
CC
= 4.5 V to 5.5 V 0.7 1.5 2.5 0.7 3.5 ns
t
PLZ
LOW to OFF-state
propagation delay
nA to nY; see Figure 6
V
CC
= 1.2 V - 10 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 2.6 5.7 0.5 6.7 ns
V
CC
= 2.3 V to 2.7 V 0.5 1.4 3.1 0.5 4.0 ns
V
CC
= 2.7 V 0.5 2.6 3.9 0.5 5.0 ns
V
CC
= 3.0 V to 3.6 V 0.5 2.2 3.7 0.5 5.0 ns
V
CC
= 4.5 V to 5.5 V 0.6 1.5 2.6 0.6 3.5 ns
C
PD
power dissipation
capacitance
per buffer; V
I
=GNDtoV
CC
[2]
V
CC
= 1.65 V to 1.95 V - 6.5 - - - pF
V
CC
= 2.3 V to 2.7 V - 6.9 - - - pF
V
CC
= 3.0 V to 3.6 V - 7.2 - - - pF
74LVC06A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 14 May 2013 7 of 15
NXP Semiconductors
74LVC06A-Q100
Hex inverter with open-drain outputs
11. Waveforms
Measurement points are given in Table 8
Logic level: V
OL
is a typical output voltage level that occurs with the output load.
Fig 6. The input nA to output nY propagation delays
mna529
t
PLZ
V
X
nY output
nA input
V
I
V
CC
V
M
V
OL
GND
t
PZL
V
M
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
X
< 2.7 V 0.5 V
CC
V
OL
+ 0.15 V
2.7 V to 3.6 V 1.5 V V
OL
+ 0.3 V
4.5 V to 5.5 V 0.5 V
CC
V
OL
+ 0.3 V
74LVC06A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 14 May 2013 8 of 15
NXP Semiconductors
74LVC06A-Q100
Hex inverter with open-drain outputs
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.2 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
2.3 V to 2.7 V V
CC
2 ns 30 pF 500 open 2 V
CC
GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
4.5 V to 5.5 V V
CC
2.5 ns 50 pF 500 open 2 V
CC
GND

74LVC06AD-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers Hex inverter with open-drain outputs
Lifecycle:
New from this manufacturer.
Delivery:
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