932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 7
932SQ420D REV J 010715
Pin Descriptions - 64 MLF (cont).
35 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
36 GNDNS PWR Ground pin for non-spreading differential outputs and logic.
37 NS_SAS0C OUT
Complementary clock of differentia non-spread ing SAS output. These are current mode outputs and external
33 ohm series resistors and 49.9 ohm shunt resistors are re
q
uired for termination.
38 NS_SAS0T OUT
True clock of differential non-spreading SAS output. These are current mode outputs. These are current
mode outputs and external 33 ohm series re sistors and 49 .9 ohm shunt resistors are required for termination.
39 NS_SAS1C OUT
Complementary clock of differential non-spreading SAS output. These are current mode outputs and external
33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
40 NS_SAS1T OUT
True clock of differential non-spreading SAS output. These are current mode outputs. These are current
mode outputs and external 33 ohm series re sistors and 49 .9 ohm shunt resistors are required for termination.
41 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits.
42 GNDNS PWR Ground pin for non-spreading differential outputs and logic.
43 CPU0C OUT
Complementary clock of differential CPU output. These are current mode o utputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are required for termination.
44 CPU0T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are required for termination.
45 CPU1C OUT
Complementary clock of differential CPU output. These are current mode o utputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are required for termination.
46 CPU1T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are re
q
uired for termination.
47 VDDCPU PWR 3.3V
p
ower for the CPU out
p
uts and lo
g
ic
48 GNDCPU PWR Ground
p
in for CPU out
p
uts and lo
g
ic.
49 CPU2C OUT
Complementary clock of differential CPU output. These are current mode o utputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are re
q
uired for termination.
50 CPU2T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are re
q
uired for termination.
51 CPU3C OUT
Complementary clock of differential CPU output. These are current mode o utputs and external 33 ohm series
resistors and 49.9 ohm shunt resistors are re
q
uired for termination.
52 CPU3T OUT
True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors
and 49.9 ohm shunt resistors are re
q
uired for termination.
53 VDDCPU PWR 3.3V
p
ower for the CPU out
p
uts and lo
g
ic
54 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
56 GND14 PWR Ground pin for 14MHz output and logic.
57 AVDD14 PWR Analog power pin for 14MHz PLL
58 VDD14 PWR Power pin for 14MHz output and logic
59 vREF14_3x/TEST_SEL I/O
14.318 MHz reference clock. 3X drive streng th as default / TEST_SEL latched input to enable test mode. Refer
to Test Clarification Table. This
p
in has a weak
(
~120Kohm
)
internal
p
ull down.
60 GND14 PWR Ground pin for 14MHz output and logic.
61 GNDXTAL PWR Ground pin for Crystal Oscillator.
62 X1_25 IN Crystal input, Nominally 25.00MHz.
63 X2_25 OUT Crystal output, Nominally 25.00MHz.
64 VDDXTAL PWR 3.3V power for the crystal oscillator.
932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 8
932SQ420D REV J 010715
Test Loads and Recommended Terminations
Single-ended Output Termination Table
Output Loads
Zo = 50
Zo =6 0
PCI/USB 1 36 43
PCI/USB 2 22 33
REF 1 39 47
REF 2 27 36
REF 3 10 20
Rs Value
(for each load)
Differential Zo
Rp Rp
HCSL Output
Buffer
932SQ420 Differential Test Loads
Rs
Rs
2pF 2pF
Differential Output Termination Table
DIF Zo (
)Iref (
)Rs (
)Rp (
)
100 475 33 50
85 412 27 42.3 or 43.2
932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 9
932SQ420D REV J 010715
Electrical Characteristics - Absolute Maximum Ratings
DC Electrical Characteristics - Differential Current Mode Outputs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Case Temperature Tc 110 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
T
A
= T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate dV/dt Scope averaging on 1 2.4 4
V/ns
1, 2, 3
Slew rate matching
dV/dt
Slew rate matching, Scope
avera
g
in
g
on
920
%
1, 2, 4
Rise/Fall Time Matching
Trf
Rise/fall matching, Scope
avera
g
in
g
off
125
ps
1, 8, 9
Voltage High VHigh 660 772 850 1
Voltage Low VLow -150 9 150 1
Max Voltage Vmax 810 1150 1, 7
Min Voltage Vmin -300 -17 1, 7
Vswing Vswing Scope averaging off 300 1446 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 351 550 mV 1, 5
Crossing Voltage (var)
-Vcross Scope averaging off 24 140 mV 1, 6
2
Measured from differential waveform
7
Includes overshoot and undershoot.
8
Measured from single-ended waveform
9
Measured with scope averaging off, using st atistics function. Variation is difference between min and max.
Measurement on single ended
signal using absolute value.
mV
Statistical measurement on
single-ended signal using
oscilloscope math function.
(
Sco
p
e avera
g
in
g
on
)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
=
2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
(100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

932SQ420DGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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