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E-L6574D

P1-P3P4-P6P7-P9P10-P10
1/10
L6574
September 2003
■ HIGH VOLTAGE RAIL UP TO 600V
■ dV/dt IMMUNITY ± 50 V/ns IN FULL
TEMPERATURE RANGE
■ DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
■ SWITCHING TIMES 80/40ns RISE/FALL
■ WITH 1nF LOAD
■ CMOS SHUT DOWN INPUT
■ UNDER VOLTAGE LOCK OUT
■ PREHEAT AND FREQUENCY SHIFTING
TIMING
■ SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PROTECTION FEATURES
■ HIGH ACCURACY CURRENT CONTROLLED
OSCILLATOR
■ INTEGRATED BOOTSTRAP DIODE
■ CLAMPING ON VS.
■ SO16, DIP 16 PACKAGES
DESCRIPTION
In order to ensure voltage ratings in excess of
600V, the L6574 is manufactured with BCD OFF
LINE technology, which makes it well suited for
lamp ballast applications.
The device is intended to drive two power MOS-
FETS, in the classical half bridge topology, ensur-
ing all the features needed to drive and properly
control a fluorescent bulb.
A dedicated timing section in the L6574 allows the
user set the necessary parameters for proper pre-
heat and ignition of the lamp.
Also, an OP AMP is available to implement closed
loop control of the lamp current during normal
lamp burning.
An integrated bootstrap section, eliminating the nor-
mally required bootstrap diode and the zener clamp-
ing on Vs, makes the L6574 well suited for low cost
applications where few additional components are
needed to build a high performance ballast.
SO16N DIP16
ORDERING NUMBERS:
L6574D L6574
CFL/TL BALLAST DRIVER PREHEAT AND DIMMING
BLOCK DIAGRAM
GND
V
REF
Imin
R
ING
VCO
EN1
V
THE
V
THE
EN2
V
S
V
BOOT
OUT
C
BOOT
LOAD
H.V.
LVG
UV
DETECTION
V
S
HVGBOOTSTRAP
DRIVER
HVG
DRIVER
LVG DRIVER
Vthpre
Ifs
C
PRE
V
REF
Imax
R
PRE
Cf
OP AMP
+
-
OPOUT
OPIN-
OPIN+
DEAD
TIME
DRIVING
LOGIC
CONTROL
LOGIC
+
-
Ipre
+
-
+
-
+
-
LEVEL
SHIFTER
D97IN493A
L6574
2/10
PIN CONNECTION (top view)
THERMAL DATA
Symbol Parameter DIP16 SO16N Unit
R
th j-amb
Thermal Resistance Junction to ambient Max. 80 120 °C/W
PIN DESCRIPTION
N° Pin Function
1 CPRE Preheat Timing Capacitor. The capacitor C
PRE
sets the preheating and the frequency shift time,
according to the relations: t
PRE
= K
PRE
· C
PRE
and t
SH
= K
FS
· C
PRE
(typ. K
PRE
= 1.5s/µF, K
FS
=
0.15s/µF). This feature is obtained by charging CPRE with two different currents. During tPRE
this current is independent of the external components, so CPRE is charged up to 3.5V (preheat
timing comparator threshold). During t
SH
the current depends on R
PRE
value (i.e. on the differ-
ence between f
PRE
and f
IGN
). In this way t
SH
is always set at 0.1t
PRE
. In steady state the voltage
at pin 1 is 5V.
2 RPRE Maximum Oscillation Frequency Setting. The resistance connected between this pin and ground
sets the fPRE value, fixing the difference between f
PRE
and f
IGN
(f
PRE
> f
IGN
). At the end of the
Start-up procedure, the effect current drown from R
PRE
is over. The voltage at this pin is fixed at
V
REF
=2V.
3 CF Oscillator Frequency Setting. The capacitor C
F
, along with to R
PRE
and R
IGN
, sets f
PRE
and f
ING
.
In normal operation this pin shows a triangular wave.
4 RIGN Minimum Oscillation Frequency Setting. The resistance connected between this pin and ground
sets the f
IGN
value. The voltage at this pin is fixed at V
REF
=2V.
5 OPout Out of the operational amplifier. To implement a feedback control loop this pin can be connected
to the RIGN pin by means an appropriate circuitry.
6 OPin- Inverting Input of the operational amplifier.
7 OPin+ Non Inverting Input of the operational amplifier.
8 EN1 Enable 1. This pin (active high), forces the device in a latched shutdown state (like in the under
voltage conditions). There are two ways to resume normal operation:
– the first is to reduce the supply voltage below the undervoltage threshold and then
increase it again until the valid supply is recognised.
– the second is activating EN2 input.
The enable 1 is especially designed for strong fault (e.g. in case of lamp disconnection).
CPRE
RPRE
CF
RING
OPOUT
OPIN+
OPIN-
1
3
2
4
5
6
7 GND
V
S
LVG
N.C.
OUT
HVG
VBOOT16
15
14
13
12
10
11
D97IN492
EN1 8 EN29
3/10
L6574
ABSOLUTE MAXIMUM RATINGS
(*) The device has an internal Clamping Zener between GND and the V
CC
pin, it must not be supplied by
a Low Impedance Voltage Source.
Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V (Human Body Model)
9 EN2 Enable 2. EN2 input (active high) restarts the start-up procedure (preheating and ignition
sequence). This features is useful if the lamp does not turn-on after the first ignition sequence .
10 GND Ground.
11 LVG Low Side Driver Output. This pin must be connected to the low side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
12 VS Supply Voltage. This pin, connected to the supply filter capacitor, is internally clamped (15.6V
typical).
13 N.C. Non Connected. This pin set a distance between the pins related to the HV and those related to
the LV side.
14 OUT High Side Driver Floating Reference. This pin must be connected close to the source of the high
side power MOS or IGBT.
15 HVG High Side Driver Output. This pin must be connected to the high side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
16 VBOOT Bootstrapped Supply Voltage. Between this pin and VS must be connected the bootstrap capac-
itor. A patented integrated circuitry replaces the external bootstrap diode, by means of a high
voltage DMOS, synchronously driven with the low side power MOSFET.
Symbol Parameter Value Unit
I
S
Supply Current (*) 25 mA
V
LVG
Low Side Output -0.3 to Vs +0.3 V
V
OUT
High Side Reference -1 to VBOOT -18 V
V
HVG
High Side Output -1 to VBOOT V
V
BOOT
Floating Supply Voltage -1 to 618 V
dV
BOOT
/dt V
BOOT
pin Slew rate (repetitive) ±50 V/ns
dV
OUT
/dt OUT pin Slew Rate (repetitive) ±50 V/ns
V
ir
Forced Input Voltage (pins Ring, Rpre) -0.3 to 5 V
V
ic
Forced Input Voltage (pins Cpre, Cf) -0.3 to 5 V
V
EN1
, V
EN2
Enable Input Voltage -0.3 to 5 V
I
EN1
, I
EN2
Enable Input Current ±3mA
V
opc
Sense Op Amp Common Mode Range -0.3 to 5 V
V
opd
Sense Op Amp Differential Mode Range ±5V
V
opo
Sense Op Amp Output Voltage (forced) 4.6 V
T
stg
, T
j
Storage Temperature -40 to +150 °C
T
amb
Ambient Temperature -40 to +125 °C
PIN DESCRIPTION (continued)
N° Pin Function
P1-P3P4-P6P7-P9P10-P10

E-L6574D

Mfr. #:
Buy E-L6574D
Manufacturer:
STMicroelectronics
Description:
Gate Drivers CFL/TL Ballast
Lifecycle:
New from this manufacturer.
Delivery:
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