SC2434SWTRT Datasheet SC2434SWTRT | P7-P9

7 2005 Semtech Corp. www.semtech.com

POWER MANAGEMENT

SC2434

Phase Current Balance

One of the fundamental challenges for multi-phase solu-

tions is to balance the phase currents to achieve the best

possible electrical and thermal performance. It is quite

easy to use the SC2434 control topology to achieve very

good phase current balance. Since the current of all the

phases passes through the same current sensing compo-

nent and the same current current of all the phases are

well balanced on pulse by pulse basis. This control results

in small and even output voltage ripple and evenly distrib-

uted thermal load. Additional advantages of using input

current mode are less sensing circuitry, less IC pins, and

less power loss on the sensing resistor comparing sensing

inductor current on the output side. Fig. 2 shows the wave-

form of inductor currents under heavy load conditions,

which clearly demonstrates the excellent performance of

SC2434 on balancing the phase current.

Applications Information (Cont.)

voltage. Fig. 3 shows the measured waveforms of power

up and power down.

Fig. 3 - Shows the measured waveforms of power up and power

down.

Over Current Protection (OCP)

When sensed current signal across the differential input

of the current amplifier exceeds 120mV typical value, OCP

circuitry will pull down the error amplifier output voltage

and also discharge the soft start capacitor. The pull down

of the error amplifier will not be released until the soft

capacitor is discharged bellow 0.3V. At this point, the

PWM outputs are reactivated and the soft start capacitor

begins to charge up again through the internal 6 Kohm

resistor. The VR will try to bring up the output voltage until

the over load or short circuit condition is removed. The

hiccup mode OCP can significantly reduce the average out-

put current under overload conditions. The hiccup timing

is controlled by the soft start time constant. Please also

notice that the OCP threshold has less than 10% toler-

ance, hence, the onset of the OCP is quite accurate. The

advantage is that the VR designer does not need to re-

serve big thermal headroom to deal with the worst-case

operation when load is over 100% but the OCP has yet not

been triggered. An RC filter is needed to filter out the

leading edge voltage spike across the current sensing re-

sistor to prevent false triggering of the OCP. The time con-

stant should be around 200nS (please see application

schematic).

Power Good

SC2434 features a power good input and an open collec-

tor power good output. The VR output voltage is scaled

down through a resistive divider and this signal is fed into

PGIN (power good input) pin. The scaled VR output volt-

age has to be bigger than 0.8V otherwise the power good

output pin is pulled down. A 5 Kohm pull-up resistor and

a 0.1uF capacitor to ground are recommended to prevent

false trigger during logic transition.

Fig. 2 - Measured inductor currents of SC2434 3-phase VR

under heavy load condition.

Under Voltage Lockout (UVLO)

During power up, when UVLO circuitry detects the chip

supply (Vcc) be bigger than 7.5V (typical value with proper

hysteresis), the bandgap voltage reference starts to charge

the external soft start capacitor through a 6 Kohm inter-

nal resistor. When soft start capacitor voltage reaches

0.5V, the output voltage starts to build up which follows

the exponential voltage profile of the soft start capacitor.

The soft start process ensures that the output voltage will

have no over shoot. During power down, UVLO will dis-

charge the soft start capacitor to shut of the PWM. The

load will absorb the energy in the output filter and no reso-

nance will occur. Hence, the CPU will not see any negative

Output

volta

Output

volta

Input

volta

Input

volta

8 2005 Semtech Corp. www.semtech.com

PRELIMINARYPOWER MANAGEMENT

SC2434

Applications Information (Cont.)

Program The Controller

Please refer to Fig. 1 and the application schematics in

this data sheet for the discussion. The resistor from pin

10 to ground, R

OSC

, programs the switching frequency. The

resistor from pin 11 to ground, R

DAC

, sets the DAC current

step size. The resistors, R

, R

, and R

DRP

set the DAC

step size, the output voltage set point, and the droop,

respectively.

MathCAD programs are available to calculate the required

parameters upon request.

Programming The Switching Frequency

The oscillator frequency can be selected first by setting the

value of R

OSC

as given below:

OSC

28.5 K

Ω

750 KHz

osc

DAC_LSB

DAC

VID

step

DAC_LSB

The per phase switching frequency is 1/3 of the oscilla-

tor frequency in three-phase mode. It is recommended

that per phase switching frequency is 200~300KHz for

good trade off of efficiency vs. transient responses.

Programming The DAC Step Size

The SC2434 allows programming of the output voltage

and the DAC step size by selecting external resistors. The

LSB of the DAC current is given by:

where V

is the trimmed voltage reference (V

= 1.5V)

and R

DAC

is the resistor from pin 11 to ground. For the

given VID step size (25mV for VRM9.0 and VRM9.2 speci-

fications), the feedback resistor can be calculated accord-

ing to the LSB of DAC current:

The above two equations are for choosing R

DAC

and R

simultaneously. The advantage of this method is that new

VID step size can be accommodated by modifying external

components while maintaining the required precision.

Choose Current Sensing Resistor According To The

Threshold Of OCP

The SC2434 controller has an over current protection (OCP)

threshold of 120mV. The normal practice is to let the

peak voltage across the sensing resistor corresponding to

full-load operation be 75% of the given OCP threshold:

drp

sense

∆

out

∆

out

phase

where I

peak

is the peak current of the output inductor. Since

the choice of sensing resistor values are limited, typically 3

mOhm, 4 mOhm, or 5 mOhm, it is recommended to choose

the sensing resistor with a bigger value than that was cal-

culated, and to use a resistive divider to get the equiva-

lent R

sense

value. The two attenuation resistors should

have value of 20 Ohm in parallel. A filter capacitor of

10nF is also needed to be across the OC+ and OC- pins of

the controller IC. Please refer the application circuit sche-

matic.

Programming The Dynamic (Active) Droop

To optimize transient responses, the SC2434 actively regu-

lates output voltage as a function of output current. At

zero current the output is positioned to the upper limit of

the regulation window. As the load increases, the output

“droops” towards the lower limit. This makes optimum

use of the output voltage error band, yielding minimum

output capacitor size and cost.

The droop is adjusted by setting the DC gain of the error

amplifier. This is done by choosing the resistor from the

ERROUT pin to the FB pin (R

DRP

) of the controller. While

the optimum value of R

DRP

may be derived experimentally,

the following equation can provide the first order calcula-

tion for given droop slope:

where R

sense

is the current sensing resistance after taken

into account of attenuation, and G

is the gain of the

current amplifier while N

phase

is number of phases being

used.

Any output interconnection impedance not within the feed-

back loop can contribute to additional drooping. This ef-

fect has to be taken into account. Usually, when testing

the regulation at different CPU pins, the results may vary

slightly by same token.

It is important to use surface mount current sensing resis-

tor to minimize the parasitic inductance for accurate cor-

relation between the above equation and the test results.

This is because the inductive contribution, which may also

sense

75%

120m

peak

9 2005 Semtech Corp. www.semtech.com

POWER MANAGEMENT

SC2434

be caused by layout inductances, may alter the PWM

comparator trip point. The value of R

DRP

may have to be

adjusted to compensate for such parasitic effects.

It must be noted that the current amplifier gain is quite

precise, with greater than 80dB of Common Mode

Rejection Ratio (CMRR). Thus the droop accuracy is

primarily based upon external components tolerances. By

employing 1% current sensing element with very low

temperature coefficient, this topology is proved to be the

best comparing the schemes of using R

dson

sensing and

using inductor winding resistance sensing. The accurate

drooping translates into minimum amount output bulk

capacitor needed to meet the voltage regulation specifica-

tions and the least system cost.

Programming The DC Level Of The Output Voltage

Kirchoff’s current law can be applied to the error

amplifier’s inverting input (see Fig. 1) to calculate R

the DC level setting resistor. For given output voltage set

point and VID setting, the resistance can be calculated

by:

Applications Information (Cont.)

p_ccm

()G

pwm

1sC

1sR

( ) 1 1.5

Fig. 4 - Loop gain and compensation of the current mode con-

troller.

where C

opam

is the equivalent internal capacitor across the

error amplifier output and the inverting input with a value

of 11pF.

The power stage transfer function under continuous

conduction mode can be approximated by:

where N

DAC_STEP

is the number of VID steps down from the

highest set point (VID=00000). For example, when VID

[4:1]=00100, N

DAC_STEP

= 4. V

is the error amplifier

output voltage and, as a first approximation, it is equal to

1..7V. Again, V

= Precision Reference Voltage = 1.5V.

The final value of R

may need to be fine tuned

experimentally after the droop resistor has been chosen.

Control Loop Compensation

The current mode control yields a power supply easy to

compensate because the power stage has first order (single

pole) behavior. The SC2434 provides internal slope

compensation to avoid sub harmonic oscillation of the

current loop. The added ramp signal has 300mV peak-to-

peak amplitude and the ramp frequency is as same as

the oscillator frequency.

As depicted in Fig. 4, the gain for the voltage feedback

loop can be expressed as a product of the power stage

gain and the compensator gain:

Loop s R

()H

p_ccm

()H

s()

Err_Amp

Verror

Loop G ain

Copam

Ccomp Rcomp

-1

Ccomp

1/(R*C)

Rdrp

POWER

STAGE

Rdrp/Rfb

Vin/( VR*Nphase)

-1

Power Stage

Compen sator

1/(E SRC )

Pole

Fsw/2

Zero

0dB

Fsw/2

-2

1/( R*C)

Vout

where G

PWM

is the low frequency gain of the power stage.

The power stage has an ESR zero, a dominant pole at

low frequency, and a pair of complex pole located at one

half of the switching frequency. The parameter used here

are defined as below:

C = output bulk capacitance

R = load resistance

= ESR of output bulk capacitor

= switching frequency

The PWM gain is defined as:

set

drp

DAC_STEP

DAC_LSB

pwm

R ! N

phase

sense·

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