ZL30113LDG1

P1-P3 P4-P6 P7-P8

Distributed

Timing For Pizza

B

ox

Timing Distribution

Bus via

B

ack

plane

BITS

A

20

MH

z

OC

X

O/

T

C

XO

P

izza

B

ox/Blade

BITS

B

ZL30138/30

R

a

t

e

C

onv

ersion

Stratum

3E

Synchronizer

Output

S

ynthesiz

ers

Frame

n Pulse

SONE

T

C

lo

cks

n-Port OC-48

F

ramer

,

Mapper,

S

erDes

Centralized System Timing And Blade

Applications

BITS

A

BITS

B

Input

Ref

er

enc

e

Timing Distribution

Bus via

Backplane

Derived

O

utput

20 MH

z

OC

X

O/

T

C

XO

Timing

Card

20 MH

z

OC

X

O/

T

C

XO

Timing

Card

Derived

O

utput

ZL30130/43

ZL30143

R

a

t

e

C

onv

ersion

Stratum

3

S

ynchr

onizer

R

a

t

e

C

onv

ersion

Stratum

3

S

ynchr

onizer

Output

S

yn

thesiz

ers

Output

S

yn

thesiz

ers

SONET/SDH

Timing Distribution

Bus via B

ack

plane

20 MHz

XTAL/

XO

Line

Card

20 MHz

XTAL/

XO

Line

Card

20 MHz

XTAL/

XO

Line

Card

ZL30146

ZL30106 ZL30146

R

a

t

e

C

onv

ersion

Line

C

ard

S

ynchr

onizer

Line

C

ard

S

ynchr

onizer

Line

C

ard

S

ynchr

onizer

Output

S

yn

thesiz

ers

O

utput

S

yn

thesiz

ers

O

utput

S

yn

thesiz

ers

n

Frame

n Pulse

SONE

T

Clocks

Frame

Pulse

1.544/2.048/

34.368/

44.736

MH

z

C

lo

ck

1G PHY

Clocks

n-Port OC-48

Framer,

Mapper,

S

erDes

n-Port DS1/E1, DS3/E3

Framer,

M

apper

PHY

Zarlink’s Timing and

S

ynchr

oniza

tion

solutions are based

on

a

founda-

tion of

over 20 years

of

expertise

in

designing leading-edge

products

that

ensure

maximum network uptime while meeting strict perfor-

mance

r

equiremen

ts

.

Highly Integrated Solutions:

Complete solutions

that

reduce

bill-of-

ma

t

er

ial

costs, board space and power

consumption

Simplify Design:

E

a

s

y-

t

o

-

a

d

o

p

t

p

ro

d

u

c

t

s

,

fully

s

u

pp

or

t

e

d by design

t

ools

,

evaluation boar

ds

,

sof

t

w

are

and

dedicated

support

t

eams

,

to

simplify and

shor

t

en

your design

cycle

Standards Compliant:

Designed

to meet the latest performance

requir

emen

ts

,

including

ITU-T

R

ec

ommenda

tion

G.8262

for

S

yn

-

chronous

E

thernet

,

to

achieve

quality of

transmission

and reliable

carrier-grade

services

Our state-of-the-art Line

Card and Timing Card synchronization

solu-

tions

increase

per

f

or

manc

e

,

reduce costs

and keep our customers

ahead

of the

technology

curv

e

.

www

. z a r

l i

n k . c o m

/ t

i m i n g

. h

t m

Information relating to

products and

services

furnished

herein b

y

Zarlink

S

emiconduc

t

or

Inc.

or

its

subsidiaries

is

believed

to be

reliable. The products,

their

spe

cific

ation

s

,

services

and

other

information

appearing

in

this

publication

are subjec

t

to change

by Zarlink

without notic

e

.

ZARLINK, ZL, ZLE

and the Zarlink

logo

are trademarks

of

Zarlink

S

emiconduc

t

or

Inc

.

© April 2009, Zarlink Semiconductor Inc. All Rights

Reserved.

Publication Number

9ZS087

P1-P3 P4-P6 P7-P8

ZL30113LDG1

Mfr. #:

Buy ZL30113LDG1

Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Pb Free Rate Conversion DPLL

Lifecycle:

New from this manufacturer.

Delivery:

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