LTC4216
10
4216fa
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switch when the TIMER pin voltage exceeds its threshold.
The timer period for C1 to charge up to the TIMER pin
threshold, V
TMR(TH)
(1.253V), is given by:
t
A
TIMER
=
2
(1)
For example, if C1 = 10nF, t
TIMER
= 6.2ms.
FB Glitch Filtering
The FB pin is used to monitor the output voltage of the
external MOSFET through a resistive divider. Any tran
-
sients on the FB pin due to the output low spikes will
pull RESET
low. To prevent RESET from generating an
unwanted system reset, the FB comparator has a glitch
filter to ride out these glitches. The filter time is 20µs for
large transients (greater than 150mV) and up to 100µs
for small transients. The relationship between glitch filter
time and the FB pin transient voltage or FB overdrive is
shown in Figure 1.
FB pin voltage rises above 0.6V, the FB comparator output
goes low and a new timing cycle starts. After a complete
timing cycle at time point 6, RESET is pulled high by the
external pull-up resistor, R5. The timer period given by
Equation (1) sets the power-good delay for RESET going
high. If the FB pin voltage stays above 0.6V for less than
a timing cycle at time point 4, the RESET output remains
low. Any overcurrent fault detected by the electronic cir
-
cuit breaker or F
AULT pin driven low externally during the
timing cycle, will also pull the TIMER pin low and RESET
output remains low.
When the device enters an undervoltage lockout condition
or the ON pin voltage drops below 0.4V, RESET is pulled
low, ignoring the FB pin voltage.
Figure 2. Output Voltage Monitor Block Diagram
Figure 3. Output Voltage Monitor
Waveforms in Normal Operation
Output Voltage Monitor
As shown in Figure 2, the output voltage is monitored
through a resistive divider, R3 and R4, connected at the
FB pin, and a FB comparator with 0.6V threshold.
The normal operation of the output voltage monitor after a
start-up cycle is shown in Figure 3. At time point 1, when the
FB pin voltage falls below 0.6V, the FB comparator output
goes high. RESET is pulled low by an internal N-channel
switch after a glitch filter delay at time point 2. When the
Figure 1. FB Comparator Glitch Filter Time vs FB Overdrive
FB OVERDRIVE (mV)
0
100
120
140
160120
4216 F01
80
60
40 80 200
40
20
0
GLITCH FILTER TIME (µs)
T
A
= 25°C
+
LOGIC
TIMER
TIMER
LTC4216**
SENSEP
0.6V
V
CC
V
IN
ON
FB
R4
R3
R
SENSE
R5
M2
M1
RESET
SENSEN GATE
+
C1
C
LOAD
**ADDITIONAL DETAILS
OMITTED FOR CLARITY
RESET
µP
V
OUT
+
4216 F02
1 2
V
OUT
V
TMR(TH)
V
FB
< 0.6V
V
FB
> 0.6V
V
FB
< 0.6V V
FB
> 0.6V
TIMER
RESET
GLITCH FILTER DELAY
3 4 5 6
POWER-GOOD
DELAY
2µA
2µA
4216 F03
LTC4216
11
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Electronic Circuit Breaker
The LTC4216 features an electronic circuit breaker function
that protects the external MOSFET against short-circuits or
excessive load current conditions on the supply. An external
sense resistor connected between SENSEP and SENSEN
pins is used to measure the load current. If the voltage
across the sense resistor exceeds the circuit breaker trip
threshold of 25mV for more than a fault filter delay, the
gate of the MOSFET is pulled low, turning it off.
The fault filter delay is determined by a capacitor, C3, con
-
nected between
the FILTER pin and ground as in Equation
(2). The FILTER pin sources 60µA pull-up current when the
sense voltage across the sense resistor exceeds 25mV.
Otherwise, it pulls down with 2.4µA. When the FILTER
pin voltage exceeds V
FILT(TH)
threshold (1.253V), there
is an internal 20µs delay before the GATE pulls low and
the FAULT pin will be pulled low. If no FILTER capacitor
is used, the filter fault delay defaults to 20µs. The circuit
breaker response time or fault filter delay with the FILTER
capacitor, C3, is given by:
t
VC
A
s
CB TRIP()
.•
=
µ
1 253 3
60
20
(2)
The FILTER capacitor, C3, should be chosen so that the
fault filter delay is not too short to trip the circuit breaker
as the MOSFET current charges up a large output load
capacitance in analog current limit during power-up. It
also should not be too long to exceed the safe operating
area (SOA) of the external MOSFET.
Intermittent overloads may exceed the current limit as in
Figure 5, but if the duration is sufficiently short, the FILTER
pin voltage may not reach the V
FILT(TH)
threshold and the
device will not shut off. To handle this situation, the FILTER
discharges with 2.4µA whenever voltage across the sense
resistor is below 25mV. Any intermittent overload with
an aggregate duty cycle of more than 4% will eventually
trip the circuit breaker. Figure 6 shows the circuit breaker
response time in seconds normalized toF as given by
Equation (3). The asymmetric charging and discharging
of FILTER is a fair gauge of MOSFET heating.
t
C
sF
D3
1 253
60
24
(/ )
.
(•)– .
µ=
(3)
Following a circuit breaker trip, the device is latched-off
and FAULT is pulled low until the fault latch is cleared by
pulling the ON pin low (< 0.4V) for at least 100µs. The
FILTER pin is pulled low by an internal N-channel switch
to discharge the capacitor quickly when the ON pin volt
-
age falls below 0.4V and pulls down with 2.4µA when the
ON pin voltage rises above 0.8V to initiate a new start-up
cycle. The new timing cycle will not start until the FILTER
pin voltage is below 0.2V. The electronic circuit breaker
is disabled during the first timing cycle upon start-up and
any short-circuit faults will be ignored.
Figure 4. A Continuous Fault Timing
Figure 5. Multiple Intermittent Overcurrent Condition
V
FILTER
CIRCUIT BREAKER TRIPS
A B
1.253V
NORMAL
MODE
FAULT
MODE
2.4µA
60µA
4216 F04
A1
I
LOAD
V
FILTER
V
GATE
CIRCUIT
BREAKER
TRIPS
1.253V
B1
CB
FAULT
CB
FAULT
CB
FAULT
A2 B2 A3 B3
25mV/R
SENSE
60µA
60µA
60µA
2.4µA
2.4µA
2.4µA
LTC4216
12
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Analog Current Limiting
In addition to an electronic circuit breaker, the LTC4216
has included a novel analog current limit (ACL) amplifier
that does not require an external compensation capacitor
at the GATE pin. The amplifier’s stability is compensated
by the large gate input capacitance (C
ISS
) of the external
MOSFET used. These MOSFETs usually have C
ISS
≥ 1nF.
However, if the MOSFET’s gate input capacitance (C
ISS
)
is too small for loop stability, then connect an external
capacitor between the GATE pin and ground to increase
the total gate capacitance to ≥ 1nF. As given by Equation
(4), the MOSFET current, I
ACL
, is limited to the analog
current limit voltage, ΔV
ACL(TH)
, 40mV typical, across
the sense resistor, R
SENSE
, connected between SENSEP
and SENSEN pins.
I
V
R
ACL
ACLTH
SENSE
=
()
(4)
The ΔV
ACL(TH)
threshold is 1.6 times higher than the
ΔV
CB(TH)
threshold (25mV typical) to provide dual level cur-
rent sensing. When the ACL amplifier servos the MOSFET
current
at ΔV
ACL(TH)
across the sense resistor, it exceeds
ΔV
CB(TH)
threshold causing the FILTER pin to charge C3
with 60µA pull-up. If the condition persists long enough
for C3 to reach the V
FILT(TH)
threshold (1.253V), GATE is
pulled low and FAULT latched low.
If the voltage across the sense resistor is greater than
ΔV
ACL(TH)
during an overload condition, the ACL amplifier
will servo GATE downwards in an attempt to control the
MOSFET current. Since the GATE pin voltage overdrives
the MOSFET in normal operation, the ACL amplifier needs
time to discharge the GATE to the threshold of the MOSFET
for gate regulation. For mild overload, the ACL amplifier
can control the MOSFET current, but in the event of a
severe overload, the MOSFET current may overshoot as
the MOSFET has large GATE overdrive initially. The GATE
is quickly discharged to ground followed by the ACL ampli
-
fier taking control. For applications that require very fast
analog
current limit recovery from the
GATE undershoot as
it discharges, connect a series resistor, R
Z
, with an exter-
nal capacitor,
C
Z
, at the GATE pin as shown in Figure 17.
The value of R
Z
should be between 10Ω and 100Ω for
optimum performance.
Soft-Start
The LTC4216 features a soft-start function that controls
the di/dt of the inrush current during power-up. As large
output load capacitors are commonly used in low voltage
applications, the normal inrush can be large enough to
glitch the load supply. With the soft-start function, the
gate of the external MOSFET is allowed to turn on very
gradually to control the inrush current flowing into the
load capacitor without causing a supply glitch.
With an external capacitor, C2, connected between the SS
pin and ground, the GATE is servoed by the ACL amplifier
to track the rate of SS ramp-up during power-up. There
are two slopes in the SS ramp-up profile: 10µA current
source pull-up for a normal ramp rate; andA current
source pull-up for a slower ramp rate. Both the SS ramp
rates are given as follows:
Normal SS Ramp Rate:
dV
dt
A
C
SS NOM()
=
µ10
2
(5)
Slower SS Ramp Rate:
dV
dt
A
C
SS SLOW()
=
µ1
2
(6)
Figure 6. Circuit Breaker Filter
Response for Intermittent Overload
OVERLOAD DUTY CYCLE, D (%)
0 20 40 60 80 100
NORMALIZED RESPONSE TIME (s/µF)
1
0.1
0.01
4216 F06
t/C3(s/µF) = 1.253/[(60 • D) – 2.4]
applicaTions inForMaTion

LTC4216IDE#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Ultralow V Hot Swap Cntr
Lifecycle:
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