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950908BFLF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
19
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
P
ower Down
W
aveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2
.
Po
wer-up latency <3ms
.
3.
Waveform shown for 100MHz
VCO Inter
nal
0ns
12
25ns
50ns
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
20
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Group Offset
W
avef
orms
Cycle Repeats
0ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
10ns
20ns
30ns
40ns
21
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Ordering Information
ICS950908
y
FLF-T
INDEX
AREA
INDEX
AREA
12
1
2
N
D
h x 45°
h x 45°
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004)
C
.10 (.004)
C
c
L
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.
20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.
40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
α
0°
8°
0°
8°
MIN
MAX
MIN
MAX
56
18.31
18.55
.
720
.730
10-0034
Referenc
e Doc.: JE
DEC P
ublicatio
n 95, MO-1
18
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Packag
e T
ype
F = SSOP
Revision Designator
(will not correlate with datasheet revision)
Device T
ype
Prefix
ICS = Standard Device
ICS XXXX
y
F LF-
T
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
950908BFLF
Mfr. #:
Buy 950908BFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
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