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950908BGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
4
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Pin Description Continued
PIN PIN PIN
# NAME TYPE
29 DDRC5/SDRAM11 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
30 DDRT5/SDRAM10 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
31 DDRC4/SDRAM9 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
32 DDRT4/SDRAM8 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
33 GND PWR Ground pin.
34 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage.
35 DDRC3/SDRAM7 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
36 DDRT3/SDRAM6 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
37 DDRC2/SDRAM5 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
38 DDRT2/SDRAM4 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
39 GND PWR Ground pin.
40 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage.
41 DDRC1/SDRAM3 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
42 DDRT1/SDRAM2 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
43 DDRC0/SDRAM1 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
44 DDRT0/SDRAM0 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output
45 BUF_IN IN Input Buffers for memory outputs.
46 FBOUT OUT Memory feed back output.
47 GND PWR Ground pin.
48 CPUT1_CS OUT True clock of differential pair 2.5V push-pull CPU outputs.
49 CPUT0_CS OUT True clock of differential pair 2.5V push-pull CPU outputs.
50 VDDCPU2.5 PWR Power pin for the CPUCLKs. 2.5V
51 VDDCPU3.3 PWR Power pin for the CPUCLKs. 3.3V
52 CPUCLKC/CPUCLKODC OUT
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
53 CPUCLKT/CPUCLKODT OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
54 GND PWR Ground pin.
55 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
56 Vtt_PWRGD#**/REF1 I/O
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
DESCRIPTION
Mode Pin - Power Management Input Control
6niP,EDOM
)tupnIdehctaL(
62niP81niP8niP
0
#DP
)tupnI(
#POTS_UPC
)tupnI(
#POTS_ICP
)tupnI(
1
#TESER
)tuptuO(
5KLCICP
)tuptuO(
2PGA
)tuptuO(
5
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
General I
2
C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
*See notes on the following page.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
6
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. B0b2 default = 0.
tiB
noitpircseD
DWP
tiB
)4:7,2(
2tiB
7tiB6tiB5tiB4tiB
KLCUPC
zHM
KLCPGA
zHM
KLCICP
zHM
%daerpS
2,1setoN
3SF2SF1SF0SF
00000 00.20100.8600.43daerpSretneC%03.0-/+
00001 00.50100.0700.53daerpSretneC%03.0-/+
00010 00.80100.2700.63daerpSretneC%03.0-/+
00011 00.11100.4700.72daerpSretneC%03.0-/+
00100 00.41100.6700.83daerpSretneC%03.0-/+
00101 00.71100.8700.93daerpSretneC%03.0-/+
00110 00.02100.0800.04daerpSretneC%03.0-/+
00111 00.32100.2800.14daerpSretneC%03.0-/+
01000 00.62100.2700.63daerpSretneC%03.0-/+
01001 00.03103.4701.73daerpSretneC%03.0-/+
01010 09.33159.6684.33daerpSretneC%03.0-/+
01011 00.04100.0700.53daerpSretneC%03.0-/+
01100 00.44100.2700.63daerpSretneC%03.0-/+
01101 00.84100.4700.73daerpSretneC%03.0-/+
01110 00.25100.6700.83daerpSretneC%03.0-/+
01111 00.65100.8700.93daerpSretneC%03.0-/+
10000 00.06100.0800.04daerpSretneC%03.0-/+
1000 1 00.46100.2800.14daerpSretneC%03.0-/+
100 10 06.66106.6603.33daerpSretneC%03.0-/+
100 11 00.07100.8600.43daerpSretneC%03.0-/+
10 100 00.57100.0700.53daerpSretneC%05.0-/+
10 10 1 00.08100.2700.63daerpSretneC%05.0-/+
10 110 00.58100.4700.73daerpSretneC%05.0-/+
10 111 00.09100.6700.83daerpSretneC%03.0-/+
11000 08.6608.6604.33daerpSretneC%03.0-/+
11001 09.00172.7636.33daerpSretneC%03.0-/+
11010 06.33108.6604.33daerpSretneC%03.0-/+
11011 04.00208.6604.33daerpSretneC%03.0-/+
11100 06.6606.6603.23daerpSnwoD%6.0-ot0
11101 00.00106.6603.33daerpSnwoD%6.0-ot0
11110 00.00206.6603.33daerpSnwoD%6.0-ot0
11111 03.33106.6603.33daerpSnwoD%6.0-ot0
3tiB
stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
elbanemurtcepsdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

950908BGLFT

Mfr. #:
Buy 950908BGLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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