19
FN6831.0
February 4, 2009
LGATE (Pins 18 and 23)
The signal going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route these traces in parallel with the trace from the
PGND pin. These two traces should be short, wide, and
away from other traces. There should be no other weak
signal traces in proximity with these traces on any layer.
BOOT (Pins 17 and 24), UGATE (Pins 16 and 25), and
PHASE (Pins 15 and 26)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
ISL62386
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6831.0
February 4, 2009
ISL62386
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
INDEX
D/2
D
E/2
E
A
B
C
0.10 BAMC
A
N
SEATING PLANE
N
6
3
2
2
3
e
1
1
0.08
SECTION "C-C"
NX b
A1
2X
C
0.15
0.15
2X
B
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
A
C
C
A3
D2
D2
E2
E2/2
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
2
NX k
NX b
8
NX L
8
8
AREA
0.10
C
/ /
(DATUM B)
(DATUM A)
AREA
INDEX
6
AREA
N
L32.5x5A
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.70 0.75 0.80 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.25 0.30 5, 8
D 5.00 BSC -
D2 3.30 3.45 3.55 7, 8
E 5.00 BSC -
E1 5.75 BSC 9
E2 3.30 3.45 3.55 7, 8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N322
Nd 8 3
Ne 8 3
Rev. 2 05/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.

ISL62386HRTZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers QD-OUTPUT SYSTEM CNTRLR 5X5 TQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet