GTLP16617MTD

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GTLP16617
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
C
L
includes probes and jig capacitance.
Test Circuit for B Outputs
C
L
includes probes and jig capacitance.
For B Port outputs, C
L
= 30 pF is used for worst case
edge rate.
Voltage Waveforms Pulse Duration
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay and Setup and Hold Times
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
All input pulses have the following characteristics: frequency = 10 MHz, t
r
= t
f
= 2 ns, Z
O
= 50. The outputs are measured one at a time with one transition
per measurement.
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GTLP16617
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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GTLP16617MTD

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers 17-Bit Syn Bus Trans
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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