STM1404 Description
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Figure 1. Logic diagram
1. V
REF
only for STM1404A; V
TPU
for STM1404B/C.
2. Normal mode: low when V
OUT
is internally switched to V
CC
and High when V
OUT
is internally switched to
battery.
3. SAL
, RST, PFO, and BLD are open drain.
Note: See Section 2: Pin descriptions on page 11 for details.
Table 2. Signal names
Vccsw
(1)
1. Normal mode: low when V
OUT
is internally switched to V
CC
and high when V
OUT
is internally switched to
battery.
V
CC
switch output
MR
Manual (push-button) reset input
PFI Power-fail input
TP
1
- TP
4
Independent physical tamper detect pins 1 through 4
V
OUT
Supply voltage output
RST
(2)
2. SAL, RST, PFO, and BLD are open drain.
Active-low reset output
PFO
(2)
Power-fail output
SAL
(2)
Security alarm output
BLD
(2)
Battery low voltage detect
V
REF
(3)
3. V
REF
only for STM1404A; V
TPU
for STM1404B/C.
1.237 V reference voltage
V
TPU
(3)
Tamper pull-up (V
CC
or V
BAT
)
V
BAT
Backup supply voltage
V
CC
Supply voltage
V
SS
Ground
AI09682a
V
CC
V
BAT
STM1404
V
SS
V
OUT
V
REF
or
V
TPU
(1)
V
CCSW
(2)
MR
SAL
(3)
BLD
(3)
PFI
TP
1
(NH)
TP
2
(NL)
TP
3
(NH)
TP
4
(NL)
PFO
(3)
RST
(3)
