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PTN3300AHF,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
PTN3300A_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 June 2008 7 of 23
NXP Semiconductors
PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
5.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
OE_N, IN_Dx and OUT_Dx signals
OE_N 25 3.3 V low-voltage
CMOS
single-ended input
Output Enable and power saving function for high-speed differential
level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero output current
When OE_N = LOW:
IN_Dx termination = 50 Ω
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D4+ makes a differential pair with IN_D4−.
The input to this pin must be AC coupled externally.
IN_D4− 47 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D4− makes a differential pair with IN_D4+.
The input to this pin must be AC coupled externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D3+ makes a differential pair with IN_D3−.
The input to this pin must be AC coupled externally.
IN_D3− 44 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D3− makes a differential pair with IN_D3+.
The input to this pin must be AC coupled externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D2+ makes a differential pair with IN_D2−.
The input to this pin must be AC coupled externally.
IN_D2− 41 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D2− makes a differential pair with IN_D2+.
The input to this pin must be AC coupled externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D1+ makes a differential pair with IN_D1−.
The input to this pin must be AC coupled externally.
IN_D1− 38 Self-biasing
differential input
Low-swing differential input from display source with PCI Express
electrical signalling. IN_D1− makes a differential pair with IN_D1+.
The input to this pin must be AC coupled externally.
OUT_D4+ 13 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D4+ makes a
differential pair with OUT_D4−. OUT_D4+ is in phase with IN_D4+.
OUT_D4− 14 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D4− makes a
differential pair with OUT_D4+. OUT_D4− is in phase with IN_D4−.
OUT_D3+ 16 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D3+ makes a
differential pair with OUT_D3−. OUT_D3+ is in phase with IN_D3+.
OUT_D3− 17 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D3− makes a
differential pair with OUT_D3+. OUT_D3− is in phase with IN_D3−.
OUT_D2+ 19 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D2+ makes a
differential pair with OUT_D2−. OUT_D2+ is in phase with IN_D2+.
OUT_D2− 20 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D2− makes a
differential pair with OUT_D2+. OUT_D2− is in phase with IN_D2−.
PTN3300A_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 June 2008 8 of 23
NXP Semiconductors
PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
[1] HWQFN48R and HWQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed
pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the
board, thermal vias need to be incorporated in the PCB in the thermal pad region.
OUT_D1+ 22 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D1+ makes a
differential pair with OUT_D1−. OUT_D1+ is in phase with IN_D1+.
OUT_D1− 23 TMDS differential
output
DVI and HDMI compliant TMDS output. OUT_D1− makes a
differential pair with OUT_D1+. OUT_D1− is in phase with IN_D1−.
HPD and DDC signals
HPD_SINK 30 5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal comes from the DVI or
HDMI sink. A HIGH value indicates that the DVI or HDMI sink is
connected; a LOW value indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated 200 kΩ pull-down resistor.
A LOW input level on this pin will automatically put the PTN3300A in
Standby mode for lowest power consumption.
HPD_SOURCE_
N
7 1.1 V CMOS
single-ended
output
0 V to 1.1 V (nominal) output signal. This is the level-shifted
logic-inverted version of the HPD_SINK signal.
SCL_SOURCE 9 single-ended 3.3 V
DDC I/O pass gate
3.3 V source-side DDC clock I/O. Pulled up by external termination to
3.3 V.
SDA_SOURCE 8 single-ended 3.3 V
DDC I/O pass gate
3.3 V source-side DDC data I/O. Pulled up by external termination to
3.3 V.
SCL_SINK 28 single-ended 5 V
DDC I/O pass gate
5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V.
SDA_SINK 29 single-ended 5 V
DDC I/O pass gate
5 V sink-side DDC data I/O. Pulled up by external termination to 5 V.
DDC_EN 32 3.3 V CMOS input Enables the DDC level shifter path.
When DDC_EN = LOW, DDC level shifter is disabled.
When DDC_EN = HIGH, DDC level shifter are enabled.
Note that HPD_SINK needs to be HIGH for the DDC channel to be
enabled.
Supply and ground
V
DD
2, 11, 15,
21, 26, 33,
40, 46
3.3 V DC supply Supply voltage; 3.3 V ± 10 %.
GND
[1]
1, 5, 12,
18, 24, 27,
31, 36, 37,
43
ground Supply ground. All ground pins must be connected to ground for
proper operation.
Feature control signals
REXT 6 analog I/O Current sense port used to provide an accurate current reference for
the differential outputs OUT_Dx. For best output voltage swing
accuracy, use of a 10 kΩ resistor (1 % tolerance) from this terminal to
GND is recommended. May also be left open-circuit or tied to either
V
DD
or GND.
Miscellaneous
n.c. 3, 4, 10,
34, 35
no connection to
the die
Not connected. May be left open-circuit or tied to GND or V
DD
either
directly or via a resistor.
Table 2. Pin description
…continued
Symbol Pin Type Description
PTN3300A_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 June 2008 9 of 23
NXP Semiconductors
PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
6. Functional description
Refer to Figure 2 “Functional diagram of PTN3300A”.
The PTN3300A level shifts four lanes of low-swing AC-coupled differential input signals to
DVI or HDMI compliant open-drain current-steering differential output signals, up to
2.25 Gbit/s per lane. It has integrated 50 Ω termination resistors for AC-coupled
differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs
and outputs, thereby minimizing power consumption. The TMDS outputs are back-power
safe to disallow current flow from a powered sink while the PTN3300A is unpowered.
The PTN3300A's DDC level-shifter allows 3.3 V source-side termination and 5 V sink-side
termination. The PTN3300A offers the back-power safe feature to disallow backdrive
current from the DDC clock and data lines when power is off or when DDC is not enabled.
An enable signal DCC_EN enables the level shifter block.
The PTN3300A also provides voltage translation for the Hot Plug Detect (HPD) signal
from 0 V/5 V on the sink side, inverting and level-shifting to 1.1 V/0 V on the source side.
PTN3300A also automatically goes into low power mode when the sink is not connected
(HPD_SINK is LOW).
The PTN3300A does not re-time any data. It contains no state machines. No inputs or
outputs of the device are latched or clocked. Because the PTN3300A acts as a
transparent level shifter, no reset is required.
6.1 Flexible and power-efficient enable and disable features
PTN3300A offers different ways to enable or disable functionality, using the Output Enable
(OE_N), Hot Plug Detect (HPD_SINK) and DDC Enable (DDC_EN) inputs. Whenever the
PTN3300A is disabled using HPD_SINK or OE_N, the device will be in Standby mode and
power consumption will be minimal; otherwise the PTN3300A will be in Active mode and
power consumption will be nominal. These three inputs each affect the operation of
PTN3300A differently: OE_N affects only the TMDS channels, DDC_EN affects only the
DDC channel, and HPD_SINK affects both TMDS and DDC channels. The following
sections and truth table describe their detailed operation.
6.1.1 Hot plug detect with power-saving feature
The HPD channel of PTN3300A in fact has a dual function: as a level-shifting inverting
buffer to pass the HPD logic signal from the display sink device (via input HPD_SINK) on
to the display source device (via output HPD_SOURCE_N), as well as a detection input
for determining when the PTN3300A will go into Standby mode to save power
consumption.
The PTN3300A will automatically disable both the TMDS and DDC channels when the
HPD input indicates that no display is connected (indicated by HPD_SINK = LOW), upon
which power consumption is minimized. The power-down behavior in HPD power-saving
mode is identical to the active disablement using both the OE_N input and the DDC_EN
input.
The logic state of the HPD_SOURCE_N output always follows the inverse logic state of
the HPD_SINK input, regardless of whether the device is in Active or Standby mode.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

PTN3300AHF,518

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Buy PTN3300AHF,518
Manufacturer:
NXP Semiconductors
Description:
IC DVI/HDMI LEVEL SHIFT 48HWQFN
Lifecycle:
New from this manufacturer.
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