1/10April 2001
■ HIGH SPEED: t
PD
= 4.5ns (TYP.) at V
CC
= 5V
■ LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
■ HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
■ 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC138
3 TO 8 LINE DECODER (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP 74AC138B
SOP 74AC138M 74AC138MTR
TSSOP 74AC138TTR
TSSOPDIP SOP
