DS1845
12 of 14
AC ELECTRICAL CHARACTERISTICS (-40°C
to 85°C
, Vcc=2.7V to 5.5V)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES
SCL clock frequency
f
SCL
Fast Mode
Standard Mode
0
0
400
100
kHz
4
Bus free time between
STOP and START
condition
t
BUF
Fast Mode
Standard Mode
1.3
4.7
ms
Hold time (repeated)
START condition
t
HD:STA
Fast Mode
Standard Mode
0.6
4.0
ms
5
Low period of SCL clock
t
LOW
Fast Mode
Standard Mode
1.3
4.7
ms
High period of SCL clock
t
HIGH
Fast Mode
Standard Mode
0.6
4.0
ms
Data hold time
t
HD:DAT
Fast Mode
Standard Mode
0
0
0.9
ms
6
Data set-up time
t
SU:DAT
Fast Mode
Standard Mode
100
250
ns
Start set-up time
t
SU:STA
Fast Mode
Standard Mode
0.6
4.7
ms
Rise time of both SDA
and SCL signals
t
R
Fast Mode
Standard Mode
20 +
0.1C
B
300
1000
ns
7
Fall time of both SDA
and SCL signals
t
F
Fast Mode
Standard Mode
20 +
0.1C
B
300
300
ns
7
Set-up time for STOP
condition
t
SU:STO
Fast Mode
Standard Mode
0.6
4.0
ms
Capacitive load for each
bus line
C
B
400 pF 7
EEPROM write time t
W
5 ms 8
NOTES:
1. All voltages are referenced to ground.
2. I
STBY
specified with V
CC
equal 3.0V and 5.0V and control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
CC
for
the corresponding inactive state.
3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
4. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
5. After this period, the first clock pulse is generated.
6. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
