853006AG www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004
8
Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
Figure 1
shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
V
BB
generated from the device is connected to the negative input.
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
V
CC
- 2V
50Ω 50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT
FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω 125Ω
84Ω 84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
The C1 capacitor should be located as close as possible to the
input pin.
PCLK
nPCLK
VBB
C1
0.1u
CLK_IN
VCC
