9
FN4631.5
November 16, 2004
ARE THERE PCB LAYOUT DESIGN BEST PRACTICES
TO FOLLOW? WHAT ARE THEY?
As with most innovative ICs performing critical tasks there
are crucial PCB layout best practices to follow for optimal
performance. PCB traces that connect each end of the
current sense resistors to the HIP1011A must not carry any
load current. This can be accomplished by two dedicated
PCB traces directly from the sense resistor to the HIP1011A,
see examples of correct and incorrect layouts in Figure 13.
Typical Applications: HIP1011A PCI Hot
Plug Controller
Introduction to HIP1011A and PCI Hot Plug
Evaluation Board
The HIP1011A is compatible with the PCI Hot Plug
specification as it is derived from the widely used HIP1011.
This device facilitates “HOT PLUGGING”, the removal or
insertion of PCI compliant cards without the need to power
down the server voltage bus. The HIP1011A controls all four,
-12V, +12V, +3.3V, +5V supplies found in PCI applications,
monitoring and protecting all against over current (OC) and
the +12V, +3.3V, +5V for under voltage (UV) conditions.
Reference the PCI Hot Plug specification available from
www.pcisig.com.
Figure 14 illustrates the PCB pattern for implementation of
the HIP1011A with 4 power MOSFETs. Additional
components for optimizing performance in particular
applications, ambient electrical noise levels or desired
features will be necessary. The ease of implementation of
the HIP1011A and MOSFETs is complemented by the small
PCB foot print necessary, since both are available in 0.150
inch SOICs. The typical application requires only 1.1 square
inches of PCB board space.
IS THERE A HIP1011A PCI HOT PLUG EVALUATION
BOARD AVAILABLE?
There is an evaluation board available through your local
Intersil sales office. The HIP1011AEVAL1 board (Figure 15)
is a simple board designed to demonstrate and evaluate the
HIP1011A using an external PWRON signal simulating a
PCI Hot Plug environment. The HIP1011AEVAL1 board
comes in 2 parts, the mother board with the HIP1011A,
MOSFETs with external components and a load board
simulating a ‘typical’ PCI load with adequate space for
modifying the existing load or to add an electronic load. Even
with a number of available test points the HIP1011A
implementation space is still very efficient. In addition, the
demo board offers adequate space to evaluate the
application note discussions found in AN9737.
CORRECT
TO HIP1011A
VS AND VISEN
TO HIP1011A
VS AND VISEN
CURRENT
SENSE RESISTOR
INCORRECT
FIGURE 13. SENSE RESISTOR LAYOUT
FIGURE 14. LAYOUT PLOT, ACTUAL SIZE (0.75in x 1.5in)
1.5in
0.75in
HIP1011A
