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71V2556SA100BGGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Absolute Maximum Ratings
(1)
100 TQFP Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
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NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.426
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
1234567
A
V
DDQ
A
6
A
4
A
8
A
16
V
DDQ
B
NC CE
2
A
3
ADV/LD
A
9
CE
2
NC
C
A
7
A
2
V
DD
A
12
A
15
NC
D
I/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
E
I/O
17
I/O
18
V
SS
V
SS
I/O
13
I/O
14
F
V
DDQ
I/O
19
V
SS
OE
V
SS
I/O
12
V
DDQ
G
I/O
20
I/O
21
BW
3
BW
2
I/O
11
I/O
10
H
I/O
22
I/O
23
V
SS
R/W
V
SS
I/O
9
I/O
8
J
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
K
I/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
L
I/O
25
I/O
27
BW
4
NC
BW
1
I/O
4
I/O
5
M
V
DDQ
I/O
28
V
SS
CEN
V
SS
I/O
3
V
DDQ
N
I/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
P
I/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
R
NC A
5
LB O
V
DD
A
13
T
NC NC A
10
A
11
A
14
NC
NC/ZZ
(5)
U
V
DDQ
NC/TMS
(3)
NC/TDI
(3)
NC/TCK
(3)
NC/TDO
(3)
NC/TR ST
(3,4)
V
DDQ
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VDD(1)
NC
NC(2)
CE
1
NC(2)
V
DD(1)
V
DD(1)
,
NC
Pin Configuration — 128K x 36, 119 BGA
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
Synchronous Truth Table
(1)
Partial Truth Table for Writes
(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

71V2556SA100BGGI

Mfr. #:
Buy 71V2556SA100BGGI
Manufacturer:
IDT
Description:
SRAM 4M X36 2.5V I/O SLOW ZBT
Lifecycle:
New from this manufacturer.
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