6.4218
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of CEN Operation
(1,2,3,4)
t
HE
t
SE
R/W
A
1
A
2
CLK
C EN
ADV/LD
ADDRESS
BW 1 - BW 4
O E
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
4875 drw 09
Q(A
1
)
B(A
2
)
C E
1
, C E
2
(2)
