4
AT49F001A(N)(T)
3365C–FLASH–9/03
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors
that can be individually erased. There are two 8K-byte parameter block sections and two main
memory blocks. The 8K-byte parameter block sections and the two main memory blocks can
be independently erased and reprogrammed. The Sector Erase command is a six bus cycle
operation. The sector address is latched on the falling WE
edge of the sixth cycle while the
30H data input command is latched at the rising edge of WE
. The sector erase starts after the
rising edge of WE
of the sixth cycle. The erase operation is internally controlled; it will auto-
matically time to completion.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a
logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to
a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle operation (please refer to the Command
Definitions table). The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE
or CE, whichever occurs
last, and the data latched on the rising edge of WE
or CE, whichever occurs first. Program-
ming is completed after the specified t
BP
cycle time. The DATA polling feature may also be
used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has
a programming lockout feature. This feature prevents programming of data in the designated
block once the feature has been enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that is used to bring up the system.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write protected region is optional to the user. The address range of the boot block is 00000
to 03FFF for the AT49F001A(N) while the address range of the boot block is 1C000 to 1FFFF
for the AT49F001A(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed with input voltage levels of 5.5V or less. Data in the main memory block can still be
changed through the regular programming method. To activate the lockout feature, a series of
six program commands to specific addresses with specific data must be performed. Please
refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if pro-
gramming of the boot block section is locked out. When the device is in the software product
identification mode (see Software Product Identification Entry and Exit sections) a read from
address location 00002H will show if programming the boot block is locked out for the
AT49F001A(N), and a read from address location 1C002H will show if programming the boot
block is locked out for the AT49F001A(N)T. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lockout feature has been activated and
the block cannot be programmed. The software product identification exit code should be used
to return to standard operation.
5
AT49F001A(N)(T)
3365C–FLASH–9/03
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot
block programming lockout by taking the RESET
pin to 12 volts. By doing this, protected boot
block data can be altered through a chip erase, sector erase or word programming. When the
RESET
pin is brought back to TTL levels the boot block programming lockout feature is again
active. This feature is not available on the AT49F001AN(T).
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F001A(N)(T) features DATA
polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. DATA
polling may begin at any time
during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F001A(N)(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49F001A(N)(T) in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V (typical), the
program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE
high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or
CE
inputs will not initiate a program cycle.
6
AT49F001A(N)(T)
3365C–FLASH–9/03
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:
A11 - A0 (Hex); A11 - A16 (don’t care).
2. Since A11 is don’t care, AAA can be replaced with 2AA.
3. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F001A(N) and 1C000H to 1FFFFH for the
AT49F001A( N)T
4. Either one of the Product ID Exit commands can be used.
5. SA = sector addresses:
For the AT49F001A(N):
SA = 00000 to 03FFF for BOOT BLOCK
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49F001A(N)T:
SA = 1C000 to 1FFFF for BOOT BLOCK
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1
SA = 18000 to 19FFF for PARAMETER BLOCK 2
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2
Command Definition (in Hex)
(1)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1 Addr D
OUT
Chip Erase 6 555 AA AAA
(2)
55 555 80 555 AA AAA 55 555 10
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
(5)
30
Byte Program 4 555 AA AAA 55 555 A0 Addr D
IN
Boot Block Lockout
(3)
6 555 AA AAA 55 555 80 555 AA AAA 55 555 40
Product ID Entry 3 555 AA AAA 55 555 90
Product ID Exit
(4)
3 555 AA AAA 55 555 F0
Product ID Exit
(4)
1 XXXX F0
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V

AT49F001ANT-55JU

Mfr. #:
Manufacturer:
Description:
IC FLASH 1M PARALLEL 32PLCC
Lifecycle:
New from this manufacturer.
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