843204AGI-01LFT Datasheet 843204AGI-01LFT, 843204AGI-01LF | P7-P9

REVISION A 11/5/15

843204I-01 DATA SHEET

7 FEMTOCLOCKS™ CRYSTAL-TO-

3.3V LVPECL FREQUENCY SYNTHESIZER

FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

Figure 4 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V and R2/

R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLK

nCLK

VCC

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 3. The XTAL_OUT pin can be left ﬂ oating. The

input edge rate can be as slow as 10ns. For LVCMOS inputs, it

is recommended that the amplitude be reduced from full swing to

half swing in order to prevent signal interference with the power

rail and to reduce noise. This conﬁ guration requires that the output

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

impedance of the driver (Ro) plus the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination

at the crystal input will attenuate the signal in half. This can be done

in one of two ways. First, R1 and R2 in parallel should equal the

transmission line impedance. For most 50Ω applications, R1 and

R2 can be 100Ω. This can also be accomplished by removing R1

and making R2 50Ω.

Zo = 50

VDD

Zo = Ro + Rs

VDD

XTAL_IN

XTAL_OUT

.1uf

FEMTOCLOCKS™ CRYSTAL-TO-

3.3V LVPECL FREQUENCY SYNTHESIZER

843204I-01 DATA SHEET

8 REVISION A 11/5/15

TERMINATION FOR 3.3V LVPECL OUTPUT

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that generate

ECL/LVPECL compatible outputs. Therefore, terminating resistors

(DC current path to ground) or current sources must be used for

functionality. These outputs are designed to drive 50Ω transmission

FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION

lines. Matched impedance techniques should be used to maximize

operating frequency and minimize signal distortion. Figures 5A

and 5B show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it would

be recommended that the board designers simulate to guarantee

compatibility across all printed circuit and clock component process

variations.

INPUTS:

CRYSTAL INPUTS

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left ﬂ oating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from XTAL_IN to ground.

CLK I

NPUT

For applications not requiring the use of a clock input, it can be left

ﬂ oating. Though not required, but for additional protection, a 1kΩ

resistor can be tied from the CLK input to ground.

CLK/nCLK I

NPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left ﬂ oating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVPECL OUTPUTS

All unused LVPECL outputs can be left ﬂ oating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left ﬂ oating or terminated.

REVISION A 11/5/15

843204I-01 DATA SHEET

9 FEMTOCLOCKS™ CRYSTAL-TO-

3.3V LVPECL FREQUENCY SYNTHESIZER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 843204I-01.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 843204I-01 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

= 3.3V + 10% = 3.63V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)

MAX

= V

CC_MAX

* I

EE_MAX

= 3.63V * 165mA = 598.95mW

• Power (outputs)

MAX

= 30mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 30mW = 120mW

Total Power

_MAX

(3.63V, with all outputs switching) = 598.95mW + 120mW = 718.95mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS

devices is 125°C.

The equation for Tj is as follows: Tj = θ

JA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ

must be used. Assumig no air ﬂ ow

and a multi-layer board, the appropriate value is 54.8°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.719W * 54.8°C/W = 124.4°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂ ow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ

FOR 48-PIN TSSOP, FORCED CONVECTION

by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 54.8°C/W 51.0°C/W 49.1°C/W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

843204AGI-01LFT

Mfr. #:

Buy 843204AGI-01LFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner CRYSTL-3.3 LVPECL FRQ SYN

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