ADP3118JCPZ-RL Datasheet ADP3118JCPZ-RL, ADP3118JRZ, ADP3118JRZ-RL | P4-P6

ADP3118

Rev. 2 | Page 4 of 14 | www.onsemi.com

ABSOLUTE MAXIMUM RATINGS

Unless otherwise specified, all voltages are referenced to PGND.

Table 2.

Parameter Rating

VCC −0.3 V to +15 V

BST −0.3 V to VCC + 15 V

BST to SW −0.3 V to +15 V

DC −5 V to +15 V

<200 ns −10 V to +25 V

DRVH

DC SW − 0.3 V to BST + 0.3 V

<200 ns SW − 2 V to BST + 0.3 V

DRVL

DC −0.3 V to VCC + 0.3 V

<200 ns −2 V to VCC + 0.3 V

IN,

−0.3 V to 6.5 V

, SOIC

2-Layer Board 123°C/W

4-Layer Board 90°C/W

, LFCSP_VD

4-Layer Board 50°C/W

Operating Ambient Temperature

Range

0°C to 85°C

Junction Temperature Range 0°C to 150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature Range

Soldering (10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 260°C

For LFCSP_VD, θ

is measured per JEDEC STD with the exposed pad

soldered to PCB.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ADP3118

Rev. 2 | Page 5 of 14 | www.onsemi.com

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

DRVH

PGND

DRVL

ADP3118

TOP VIEW

(Not to Scale)

05452-002

Figure 2. 8-Lead SOIC Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched.

2 IN Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this

pin low turns on the low-side driver; pulling it high turns on the high-side driver.

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4 VCC Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.

5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.

7 SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return

for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the

lower MOSFET until the voltage is below ~1 V.

8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

ADP3118

Rev. 2 | Page 6 of 14 | www.onsemi.com

TIMING CHARACTERISTICS

tpdl

90%

10%

DRVH

DRVL

tpdh

05452-004

Figure 3. Output Disable Timing Diagram

DRVH – SW

DRVL

pdl

DRVL

pdl

DRVH

pdh

DRVH

pdh

DRVL

05452-005

Figure 4. Timing Diagram—Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

ADP3118JCPZ-RL

Mfr. #:

Buy ADP3118JCPZ-RL

Manufacturer:

ON Semiconductor

Description:

IC MOSFET DRIVER DUAL 12V 8LFCSP

Lifecycle:

New from this manufacturer.

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ADP3118JCPZ-RL

ADP3118JCPZ-RL

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