4
AT93C86A [Preliminary]
3408DSEEPR04/04
Note: 1. This parameter is characterized and is not 100% tested.
AC Characteristics
Applicable over recommended operating range from T
AI
= 40°C to + 85°C, T
AE
= 40°C to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
f
SK
SK Clock
Frequency
4.5V V
CC
5.5V
2.7V V
CC
5.5V
1.8V V
CC
5.5V
0
0
0
2
1
0.25
MHz
t
SKH
SK High Time
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
SKL
SK Low Time
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
CS
Minimum CS
Low Time
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
CSS
CS Setup Time Relative to SK
2.7V V
CC
5.5V
1.8V V
CC
5.5V
50
200
ns
t
DIS
DI Setup Time Relative to SK
2.7V V
CC
5.5V
1.8V V
CC
5.5V
100
400
ns
t
CSH
CS Hold Time Relative to SK 0 ns
t
DIH
DI Hold Time Relative to SK
2.7V V
CC
5.5V
1.8V V
CC
5.5V
100
400
ns
t
PD1
Output Delay to 1 AC Test
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
PD0
Output Delay to 0 AC Test
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
SV
CS to Status Valid AC Test
2.7V V
CC
5.5V
1.8V V
CC
5.5V
250
1000
ns
t
DF
CS to DO in High
Impedance
AC Test
CS = V
IL
2.7V V
CC
5.5V
1.8V V
CC
5.5V
150
400
ns
t
WP
Write Cycle Time
10 ms
4.5V V
CC
5.5V 0.1 4 ms
Endurance
(1)
5.0V, 25°C, Page Mode 1M Write Cycles
5
AT93C86A [Preliminary]
3408DSEEPR04/04
Functional
Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic 1) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the ddress code for the memory
location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic 0) precedes the 8- or 16-bit data output string. The AT93C86A sup-
ports sequential read operations. The device will automatically increment the internal
address pointer and clock out the next memory location as long as CS is held high. In
this case, the dummy bit (logic 0) will not be clocked out between memory locations,
thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or V
CC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical 1 state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
A logic 1 at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle t
WP
starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (t
CS
). A logic 0 at DO indicates that programming is still in progress. A logic
Instruction Set for the AT93C86A
Instruction SB Op Code
Address Data
Commentsx 8 x 16 x 8 x 16
READ 1 10 A
10
A
0
A
9
A
0
Reads data stored in memory,
at specified address.
EWEN 1 00 11XXXXXXXX 11XXXXXXXX Write enable must precede all
programming modes.
ERASE 1 11 A
10
A
0
A
9
A
0
Erases memory location A
n
A
0
.
WRITE 1 01 A
10
A
0
A
9
A
0
D
7
D
0
D
15
D
0
Writes memory location A
n
A
0
.
ERAL 1 00 10XXXXXXXX 10XXXXXXXX Erases all memory locations.
Valid only at V
CC
= 4.5V to 5.5V.
WRAL 1 00 01XXXXXXXX 01XXXXXXXX D
7
D
0
D
15
D
0
Writes all memory locations.
Valid when V
CC
= 4.5V to 5.5V and
Disable Register cleared.
EWDS 1 00 00XXXXXXXX 00XXXXXXXX Disables all programming instructions.
6
AT93C86A [Preliminary]
3408DSEEPR04/04
1 indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle t
WP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic 1 state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept low for
a minimum of 250 ns (t
CS
). The ERAL instruction is valid only at V
CC
= 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
The WRAL instruction is valid only at V
CC
= 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.

AT93C86A-10SI-2.7

Mfr. #:
Manufacturer:
Description:
IC EEPROM 16K SPI 2MHZ 8SOIC
Lifecycle:
New from this manufacturer.
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