LTC2634HUD-HMI10#TRPBF Datasheet LTC2634IUD-LZ12#PBF, LTC2634HUD-LZ8#PBF, LTC2634IUD-HMX10#PBF | P19-P21

LTC2634

2634fc

operation

The LTC2634 is a family of quad voltage output DACs in

16-lead QFN and 10-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10- and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), and full-

scale voltage (2.5V or 4.096V) are available. The LTC2634

is controlled using a 3-wire SPI/MICROWIRE compatible

interface.

Power-On Reset

The LTC2634-HZ/LTC2634-LZ clear the output to zero-scale

when power is ﬁrst applied, making system initialization

consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2634

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2634-HMI/LTC2634-HMX/LTC2634-LMI/

TC2634

-LMX provide an alternative reset, setting the

output to mid-scale when power is ﬁrst applied. The

LTC2634-LMI and LTC2634-HMI power up in internal

reference mode, with the output set to a mid-scale volt-

age of 1.25V and 2.048V, respectively. The LTC2634-LMX

and LTC2634-HMX power up in external reference mode,

with the output set to mid-scale of the external reference.

Default reference mode selection is described in the Refer-

ence Modes section.

Power Supply Sequencing

The voltage at REF (Pin 10, QFN/Pin 7, MSOP) must be

kept within the range –0.3V ≤ V

REF

≤ V

+ 0.3V (see

Absolute Maximum Ratings). Particular care should be

taken to observe these limits during power supply turn-

on and turn-off sequences, when the voltage at V

is in

transition.

Transfer Function

The digital-to-analog transfer function is:

V V V

OUT IDEAL

REF REFLO REFLO( )

–=













( )

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and V

REF

is either 2.5V

(LTC2634-LMI/LTC2634-LMX/LTC2634-LZ) or 4.096V

(LTC2634-HMI/LTC2634-HMX/LTC2634-HZ) when in

internal reference mode, and the voltage at REF when in

external reference mode. The resulting DAC output span

is 0V to V

REF

, as it is necessary to tie REFLO to GND.

Serial Interface

The CS/LD input is level-triggered. When this input is

taken low, it acts as a chip-select signal, enabling the SDI

and SCK buffers and the input shift register. Data (SDI

input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded ﬁrst; then the 4-bit

DAC address, A3-A0; and ﬁnally the 16-bit data word.

The data word comprises the 12-, 10- or 8-bit input code,

ordered MSB to LSB, followed by 4, 6 or 8 don’t-care

bits (LTC2634-12/LTC2634-10/LTC2634-8 respectively;

see Figure 2). Data can only be transferred to the device

when the CS/LD signal is low, beginning on the ﬁrst rising

edge of SCK. SCK may be high or low at the falling edge

LTC2634

2634fc

operation

COMMAND

Input Word (LTC2634-12)

ADDRESS DATA (12 BITS + 4 DON’T CARE BITS)

D9D10D11

D7 D6 D5 D4

D1 D0 X X X

MSB

LSB

COMMAND

Input Word (LTC2634-10)

ADDRESS DATA (10 BITS + 6 DON’T CARE BITS)

D7D8D9

D5 D4 D3 D2

X X X X X

MSB

LSB

COMMAND

Input Word (LTC2634-8)

ADDRESS DATA (8 BITS + 8 DON’T CARE BITS)

D5D6D7

D3 D2 D1 D0

X X X X X

MSB

LSB

2634 F02

Table 1. Command Codes

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register n

0 0 0 1 Update (Power Up) DAC Register n

0 0 1 0 Write to Input Register n, Update (Power Up) All

0 0 1 1 Write to and Update (Power Up) DAC Register n

0 1 0 0 Power-Down DAC n

0 1 0 1 Power-Down Chip (All DACs and Reference)

0 1 1 0 Select Internal Reference (Power-Up Reference)

0 1 1 1 Select External Reference (Power-Down Internal

Reference)

1 1 1 1 No Operation

*Command codes not shown are reserved and should not be used.

Table 2. Address Codes

ADDRESS (n)*

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

1 1 1 1 All DACs

* Address codes not shown are reserved and should not be used.

Figure 2. Command and Data Input Format

of CS/LD. The rising edge of CS/LD ends the data transfer

and causes the device to execute the command speciﬁed

in the 24-bit input sequence. The complete sequence is

shown in Figure 3a.

The command (C3-C0) and address (A3-A0) assignments

are shown in Tables 1 and 2. The ﬁrst four commands

in Table 1 consist of write and update operation. A write

operation loads a 16-bit data word from the 24-bit shift

update operation copies the data word from the input

8-bit input code, and is converted to an analog voltage at

the DAC output. Write to and update combines the ﬁrst

two commands. The update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

LTC2634

2634fc

operation

While the minimum input sequence is 24 bits, it may

optionally be extended to 32 bits to accommodate micro-

processors that

have a minimum word width of 16 bits

(2 bytes). To use the 32-bit width, 8 don’t care bits

must be transferred to the device ﬁrst, followed by the

24-bit sequence described. Figure 3b shows the 32-bit

sequence.

The 16-bit data word is ignored for all commands that do

not include a write operation.

Daisy-Chain Operation (QFN Package)

The serial output of the shift register appears at the SDO

pin on the QFN package. Data transferred to the device

from the SDI input is delayed 32 SCK rising edges before

being output at the next SCK falling edge, therefore, daisy

chaining multiple LTC2634 DACs requires 32-bit data

write cycles.

The SDO output can be used to facilitate control of multiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDI and CS/LD). Such a “daisy-chain” series is conﬁgured

by connecting SDO of each upstream device to SDI of the

next device in the chain. The shift registers of the devices

are thus connected in series, effectively forming a single

input shift register which extends through the entire chain.

Because of this, the devices can be addressed and controlled

individually by simply concatenating their input words;

the ﬁrst instruction addresses the last device in the chain

and so forth. The SCK and CS/LD signals are common to

all devices in the series. Figure 5 shows a block diagram

for daisy-chain operation.

In use, CS/LD is ﬁrst taken low. Then the concatenated

input data is transferred to the chain, using SDI of the

ﬁrst device as the data input. When the data transfer is

complete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the no-operation command

(1111) for the other devices in the chain.

Reference Modes

For applications where an accurate external reference is

either not available, or not desirable due to limited space,

the LTC2634 has a low noise, user-selectable, integrated

reference. The integrated reference voltage is internally

ampliﬁed by 2x to provide the full-scale DAC output volt-

age range. The LTC2634-LMI/LTC2634-LMX/LTC2634-LZ

provides a full-scale DAC output of 2.5V. The LTC2634-

MI/LTC2634-HMX/LTC2634-HZ provides a full-scale

DAC output of 4.096V. The internal reference can be

useful in applications where the supply voltage is poorly

regulated. Internal Reference mode can be selected by

using command 0110b, and is the power-on default for

LTC2634-HZ/LTC2634-LZ, as well as for LTC2634-HMI/

LTC2634-LMI.

The 10ppm/°C, 1.25V (LTC2634-LMI/LTC2634-LMX/

LTC2634-LZ) or 2.048V (LTC2634-HMI/LTC2634-HMX/

LTC2634-HZ) internal reference is available at the REF pin.

Adding bypass capacitance to the REF pin will improve

noise performance; 0.1µF is recommended, and up to 10µF

can be driven without oscillation. The REF output must be

buffered when driving an external DC load current.

Alternatively, the DAC can operate in external reference

mode using command 0111b. In this mode, an input voltage

supplied externally to the REF pin provides the reference

(1V ≤ V

REF

≤ V

) and the supply current is reduced. The

external reference voltage supplied sets the full-scale DAC

output voltage. External reference mode is the power-on

default for LTC2634-HMX/LTC2634-LMX.

The reference mode of LTC2634-HZ/LTC2634-LZ/

TC2634

-HMI/LTC2634-LMI (internal reference power-on

default), can be changed by software command after power

up. The same is true for LTC2634-HMX/-LMX (external

reference power-on default).

The LTC2634’s QFN package offers a REFLO pin for the

negative reference. REFLO must be connected to GND.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

LTC2634HUD-HMI10#TRPBF

Mfr. #:

Buy LTC2634HUD-HMI10#TRPBF

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 10-Bit SPI Quad DAC (4.096V ref, Reset to Mid-Scale, Int. Ref)

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