10
FN6140.2
June 15, 2006
ACK - (Acknowledge Input). A “low” on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
INTR - (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK
is a “one”, OBF is a “one” and INTE is a “one”. It is reset
by the falling edge of WR
.
INTE A
Controlled by Bit Set/Reset of PC6.
INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF
to the peripheral device, generates an ACK from the
peripheral device and then latch data into the peripheral device
on the rising edge of OBF
.
FIGURE 6. MODE 1 INPUT
FIGURE 7. MODE 1 (STROBED INPUT)
1
D7
0
D6
1
D5
1
D4
1/0
D3
D2 D1 D0
CONTROL WORD
MODE 1 (PORT A)
PC4
8
IBFAPC5
INTE
A
PA7-PA0
STBA
INTRA
PC3
PC6, PC7
I/O
2
RD
PC6, PC7
1 = INPUT
0 = OUTPUT
1
D7
D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT B)
PC2
8
IBFBPC1
INTE
B
PB7-PB0
STBB
INTRB
PC0
RD
11
tST
STB
INTR
RD
INPUT FROM
IBF
PERIPHERAL
tSIB
tSIT
tPH
tPS
tRIT
tRIB
FIGURE 8. MODE 1 OUTPUT
1
D7
0
D6
1
D5
1
D4
1/0
D3
D2 D1 D0
CONTROL WORD
MODE 1 (PORT A)
PC7
8
ACKAPC6
PA7-PA0
OBFA
INTRA
PC3
PC4, PC5
2
WR
PC4, PC5
1 = INPUT
0 = OUTPUT
1
D7
D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT B)
PC1
8
ACKBPC2
INTE
B
PB7-PB0
OBFB
INTRB
PC0
WR
10
INTE
A
MS82C55A, MQ82C55A, MP82C55A
11
FN6140.2
June 15, 2006
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
Used in Group A only
One 8-bit, bidirectional bus Port (Port A) and a 5-bit
control Port (Port C)
Both inputs and outputs are latched
The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A)
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
Output Operations
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK
- (Acknowledge). A “low” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF
).
Controlled by bit set/reset of PC4.
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
FIGURE 9. MODE 1 (STROBED OUTPUT)
tWOB
tWB
tAK tAIT
tAOB
tWIT
OBF
WR
INTR
ACK
OUTPUT
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
1
D7
0
D6
1
D5
1
D4
1/0
D3
D2 D1 D0
CONTROL WORD
PORT A - (STROBED INPUT)
PC4
8
OBFB
PA7-PA0
STBA
INTRB
PC0
PC6, PC7
2
WR
PC6, PC7
1 = INPUT
0 = OUTPUT
PORT B - (STROBED OUTPUT)
8
IIBFA
PC5
INTRA
PC3
ACKB
PC2
I/O
PC1
PB7, PB0
RD
10 1
D7
0
D6
1
D5
0
D4
1/0
D3
D2 D1 D0
CONTROL WORD
PORT A - (STROBED OUTPUT)
PC7
8
STBB
PA7-PA0
OBFA
INTRB
PC0
PC4, PC5
2
RD
PC4, PC5
1 = INPUT
0 = OUTPUT
PORT B - (STROBED INPUT)
8
ACKA
PC6
INTRA
PC3
IBFB
PC1
I/O
PC2
PB7, PB0
WR
11
MS82C55A, MQ82C55A, MP82C55A
12
FN6140.2
June 15, 2006
FIGURE 11. MODE CONTROL WORD FIGURE 12. MODE 2
NOTE: Any sequence where WR
occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK
WR)
FIGURE 13. MODE 2 (BIDIRECTIONAL)
1
D7
D6 D5 D4 D3 D2 D1 D0
C
ONTROL WORD
1/0 1/011/0
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
PC7
OBFA
PC6
INTE
PA7-PA0
ACKA
IBFA
PC4
WR
INTE
RD
PC3
PC5
PC2-PC0
1
2
8
STB
A
3
I/O
INTRA
tWOB
tAOB
tAK
tAD
tKD
tPH
tPS
tSIB
tST
OBF
WR
INTR
ACK
IBF
STB
PERIPHERAL
BUS
RD
tRIB
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
DATA FROM
CPU TO 82C55A
MS82C55A, MQ82C55A, MP82C55A

CMQ82C55AZ96

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Interface - I/O Expanders PERI PRG-I/O 5V 8MHZ COMOKIPLACEMENT
Lifecycle:
New from this manufacturer.
Delivery:
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