Voltage Supervisor
The voltage supervisor monitors the V
DD
supply. A
220µs reset pulse (t
W
) is used internally to keep the
device inactive during power-on or power-off of the
V
DD
supply. See Figure 2.
The IC card interface remains inactive regardless of the
levels on the command lines until duration t
W
after V
DD
has reached a level higher than V
TH2
+ V
HYS2
. When
V
DD
falls below V
TH2
, the device executes a card
deactivation sequence if the card interface is active.
Clock Circuitry
The card clock signal (CLKA/CLKB) is derived from a
clock signal input to XTAL1 or from a crystal operating
at up to 20MHz connected between XTAL1 and XTAL2.
The output clock frequency of CLK_ is selectable
through inputs CLKDIV1 and CLKDIV2. The CLK signal
frequency can be f
XTAL
, f
XTAL
/2, f
XTAL
/4, or f
XTAL
/8.
See Table 1 for the frequency generated on the CLK_
signal given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK_ is eight periods of XTAL1.
The frequency change is synchronous: during a transi-
tion of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The f
XTAL
duty factor depends on the input signal on
XTAL1. To reach a 45% to 55% duty factor on CLK_,
XTAL1 should have a 48% to 52% duty factor with tran-
sition times less than 5% of the period.
With a crystal, the duty factor on CLK_ can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK_ is guaranteed between 45% and 55% of
the clock period.
I/O Transceivers
I/O_ and I/OIN are pulled high with an 11kΩ resistor
(I/O_ to V
CC_
and I/OIN to V
DD
) in the inactive state.
The first side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay t
D(EDGE)
, an n
transistor on the slave side is turned on, thus transmit-
ting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay t
PU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high tran-
sitions. After the duration of t
PU
, the output voltage
depends only on the internal pullup resistor and the
DS8005
Smart Card Interface
10 ______________________________________________________________________________________
V
DD
ALARM
(INTERNAL SIGNAL)
POWER ON
t
W
t
W
POWER OFF
V
TH2
+ V
HYS2
V
TH2
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
Table 1. Clock Frequency Selection
CLKDIV1 CLKDIV2 f
CLK
0 0 f
XTAL
/8
0 1 f
XTAL
/4
1 1 f
XTAL
/2
1 0 f
XTAL
DS8005
Smart Card Interface
______________________________________________________________________________________ 11
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
Inactive Mode
The device powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
All card contacts are inactive (approximately 200Ω to
GND).
The I/OIN pin in the high-impedance state (11kΩ
pullup resistor to V
DD
).
Voltage generators are stopped.
XTAL oscillator is running (if included in the device).
Voltage supervisor is active.
The internal oscillator is running at its low frequency.
Activation Sequence
After power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
If the card is in the reader (if PRES_ is active), the host
microcontroller can begin an activation sequence (start
a card session) by pulling CMDVCC low. The following
events form an activation sequence (Figure 3):
1) CMDVCC is pulled low.
2) The internal oscillator changes to high frequency (t
0
).
3) The voltage generator is started (between t
0
and t
1
).
ATR
CMDVCC
RST_
RSTIN
CLK_
V
CC_
I/O_
I/OIN
t
0
t
1
t
2
t
3
t
4
t
5
= t
ACT
Figure 3. Activation Sequence Using RSTIN and CMDVCC
Table 2. Card Presence Indication
SEL_AB OFF CMDVCC STATUS
Low High High Card A present.
Low Low High Card A not present.
High High High Card B present.
High Low High Card B not present.
SEL_AB OFF2 CMDVCC STATUS
Low High High Card B present.
Low Low High Card B not present.
High High High Card A present.
High Low High Card A not present.
DS8005
4) V
CC_
rises from 0 to 5V, 3V, or 1.8V with a controlled
slope (t
2
= t
1
+ 1.5 × T). T is 64 times the internal
oscillator period (approximately 25µs).
5) I/O_ pin is enabled (t
3
= t
1
+ 4T) (they were previ-
ously pulled low).
6) The CLK_ signal is applied to the C3 contact (t
4
).
7) RST_ is enabled (t
5
= t
1
+ 7T).
To apply the clock to the card interface:
1) Set RSTIN high.
2) Set CMDVCC low.
3) Set RSTIN low between t
3
and t
5
; CLK_ now starts.
4) RST_ stays low until t
5
, then RST becomes the copy
of RSTIN.
5) RSTIN has no further effect on CLK_ after t
5
.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK_ starts at t
3
(minimum
200ns after the transition on I/O; see Figure 4); after t
5
,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
Active Mode
When the activation sequence is completed, the card
interface is in active mode. The host microcontroller
and the smart card exchange data on the I/O lines.
Deactivation Sequence
When a session is completed, the host microcontroller
sets the CMDVCC line high to execute an automatic
deactivation sequence and returns the card interface to
the inactive mode (Figure 5).
1) RST_ goes low (t
10
).
2) CLK_ is held low (t
12
= t
10
+ 0.5 × T) where T is 64
times the period of the internal oscillator (approxi-
mately 25µs).
3) I/O_ pin is pulled low (t
13
= t
10
+ T).
4) V
CC
starts to fall (t
14
= t
10
+ 1.5 × T).
5) When V
CC_
reaches its inactive state, the deactiva-
tion sequence is complete (at t
DE
).
6) All card contacts become low impedance to GND;
I/OIN remains at V
DD
(pulled up through an 11kΩ
resistor).
7) The internal oscillator returns to its lower frequency.
V
CC
Generator
Each V
CC_
generator has a capacity to supply up to
80mA continuously at 5V, 65mA at 3V, and 30mA at
1.8V. An internal overload detector triggers at approxi-
mately 120mA. Current samples to the detector are fil-
tered. This allows spurious current pulses (with a
duration of a few µs) up to 200mA to be drawn without
causing deactivation. The average current must stay
below the specified maximum current value. To main-
tain V
CC
voltage accuracy, a 100nF capacitor (with an
ESR < 100mΩ) should be connected to CGND and
placed near the V
CC_
pin, and a 100nF or 220nF
capacitor (220nF is the best choice) with the same ESR
should be connected to CGND and placed near the
smart card reader’s C1 contact.
Fault Detection
The following fault conditions are monitored:
Short-circuit or high current on V
CC_
Removal of a card during a transaction
•V
DD
dropping
Card voltage generator operating out of the specified
values (V
DDA
too low or current consumption too
high)
Overheating
There are two different cases (Figure 6):
CMDVCC High Outside a Card Session. Output
OFF_ is low if a card is not in the card reader and
high if a card is in the reader. The V
DD
supply is mon-
itored—a decrease in input voltage generates an
internal power-on reset pulse but does not affect the
OFF_ signal. Short-circuit and temperature detection
is disabled because the card is not powered up.
CMDVCC Low Within a Card Session. Output OFF_
goes low when a fault condition is detected, and an
emergency deactivation is performed automatically
(Figure 7). When the system controller resets CMD-
VCC to high, it may sense the OFF_ level again after
completing the deactivation sequence. This distin-
guishes between a card extraction and a hardware
problem (OFF_ goes high again if a card is present).
Depending on the connector’s card-present switch
(normally closed or normally open) and the mechani-
cal characteristics of the switch, bouncing can occur
on the PRES_ signals at card insertion or withdrawal.
The device has a debounce feature with an 8ms typical
duration (Figure 6). When a card is inserted, output
OFF_ goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES_ and output OFF_ goes low.
Smart Card Interface
12 ______________________________________________________________________________________

DS8005-RJX+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC DUAL SMARTCARD AFE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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