DC919A-I Datasheet DC919A-C, DC919A-I, DC919A-A | P1-P3

dc919af

DEMO MANUAL DC919A

DESCRIPTION

LTC2207, LTC2206, LTC2205,

LTC2204, LTC2203, LTC2202, LTC2201

16-Bit/14-Bit 10Msps to 105Msps ADCs

Demonstration circuit 919A supports members of a family

of 16-bit/14-bit 10Msps to 105Msps ADCs. Each assembly

features one of the following devices: LTC

2207, LTC2206,

LTC2205, LTC2204, LTC2203, LTC2202, or LTC2201 high

speed, high dynamic range ADCs.

Other members of this family include the LTC2208/

LTC2208-14 16-bit/14-bit 130Msps ADC with LVDS out-

puts. These 9mm × 9mm QFN devices are supported by

Demonstration circuit 854 (CMOS outputs) or by Dem-

onstration circuit 996 (LVDS outputs).

Several versions of the 919A demo board supporting a

single-ended clock input, specifically targeted for use

with the 25Msps LTC2203, 20Msps LTC2201 and 10Msps

L, LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks

and QuikEval and PScope are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

LTC2202 A/D converters, are listed in Table 1. LTC2204,

LTC2205, LTC2206 and LTC2207 have differential clock

inputs but use a single-ended clock input for evaluation

with the DC input on the DC919A board. Depending on the

required sample rate and input frequency, the DC919A is

supplied with the appropriate ADC and with an optimized

input circuit. The circuitry on the analog inputs is optimized

for analog input frequencies from DC to 70MHz or from

1MHz to 70MHz if using the transformer coupled input. For

higher input frequencies, contact the factory for support.

Design files for this circuit board are available at

http://www.linear.com/demo

Table 1. DC919A Variants

DC919 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

919A-A LTC2207 16-Bit 105Msps DC - 70MHz

919A-B LTC2206 16-Bit 80Msps DC - 70MHz

919A-C LTC2205 16-Bit 65Msps DC - 70MHz

919A-D LTC2204 16-Bit 40Msps DC -70MHz

919A-E LTC2203 16-Bit 25Msps DC - 70MHz

919A-F LTC2202 16-Bit 10Msps DC - 70MHz

919A-G LTC2207-14 14-Bit 105Msps DC -70MHz

919A-H LTC2206-14 14-Bit 80Msps DC - 70MHz

919A-I LTC2205-14 14-Bit 65Msps DC - 70MHz

919A-J LTC2201 16-Bit 20Msps DC - 70MHz

PERFORMANCE SUMMARY

= 25°C)

PARAMETER CONDITION VALUE

Supply Voltage Depending on Sampling Rate and the A/D Converter Provided, this

Supply Must Provide Up to 500mA.

Optimized for 3.3V

[3.15V ↔ 3.45V Min/Max]

Analog Input Range Depending on PGA Pin Voltage 1.5V

P-P

to 2.25V

P-P

Logic Input Voltages Minimum Logic High 2.4V

Maximum Logic Low 0.8V

Logic Output Voltage

(74VCX245 Output Buffer, V

= 2.5V)

Minimum Logic High at –1.6mA 2.3V (33Ω Series Terminations)

Maximum Logic Low at 1.6mA 0.7V (33Ω Series Terminations)

Sampling Frequency (Convert Clock Frequency) See Table 1

dc919af

DEMO MANUAL DC919A

QUICK START PROCEDURE

Demonstration circuit 919A is easy to set up to evaluate

the performance of the LTC2207, LTC2206, LTC2205,

LTC2204, LTC2203, or LTC2202 A/D converters. Refer to

Figure 1 for proper measurement equipment setup and

follow this procedure:

Setup

If a DC718 QuikEval™ II Data Analysis and Collection

System was supplied with the DC919A demonstration

circuit, follow the DC718 Quick Start Guide to install the

required software and for connecting the DC718 to the

DC919A to a PC.

DC919A Demonstration Circuit Board Jumpers

The DC919A demonstration circuit board should have

the following jumper settings as default: (as per Figure 1)

JP1: Output clock polarity: GND

JP2: SENSE: VDD, (Internal reference)

JP3: PGA: GND 2.25V range

JP4: RAND: GND Not randomized

JP5: SHDN: GND Not shutdown

JP6: DITH: GND No internal dithering

Applying Power and Signals to the DC919A

Demonstration Circuit

If a DC718 is used to acquire data from the DC919A, the

DC718 must FIRST be connected to a powered USB port

or provided an external 6V to 9V BEFORE applying 3.3V

across the pins marked “+3.3V” and “PWR GND” on the

DC919A. The DC919A demonstration circuit requires up

to 500mA depending on the sampling rate and the A/D

converter supplied.

The DC718 data collection board is powered by the USB

cable and does not require an external power supply unless

it must be connected to the PC through an unpowered hub

in which case it must be supplied an external 6V to 9V on

turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.

Encode Clock

NOTE: This is a logic compatible input, contrary to the

majority of Linear Technology ADC demo boards. It is not

terminated with 50Ω.

Apply an encode clock to the SMA connector on the DC919A

demonstration circuit board marked “J3 ENCODE INPUT”.

For the best noise performance, the ENCODE INPUT

must be driven with a very low jitter source. A low jitter

3.3V oscillator with direct connection through a barrel is

recommended.

If using a sinusoidal generator, the amplitude should be

as large as possible, up to 3V

P-P

or 13dBm, filtered and

terminated with a 50Ω thru-terminator. If a generator

with 50Ω output impedance is connected via a cable, it

is recommended that a thru-terminator be used. However,

below 15MHz, it is recommended that a square wave

drive be used.

If a sinusoidal ground referenced signal, or an AC-coupled

signal is used, 1.5V to 1.7V DC bias must be introduced

via a bias tee.

DC919A has provision for a popular surface mount oscil-

lator form and some population options to select this as

the clock source. (Please see schematic.)

If only sinusoidal or clipped sinusoid signal sources are

available as the clock source for scenarios involving sam-

pling rates less than 15Msps to 20Msps, it is recommended

PERFORMANCE SUMMARY

= 25°C)

Convert Clock Level 50Ω Source Impedance, AC-Coupled or Ground Referenced (Convert

Clock Input Is Capacitor Coupled on Board and Terminated with 50Ω.)

P-P

↔ 2.5V

P-P

Sine Wave or

Square Wave

Resolution See Table 1

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

dc919af

DEMO MANUAL DC919A

QUICK START PROCEDURE

Figure 1. DC919A Setup

that a divide by 4 or divide by 8 be used. If the converter

is to be used at very low sampling rates approaching the

minimum, a higher divide ratio may be required. This is

especially important if undersampling.

If you want to use these converters at less than the minimum

sampling rate, it is recommended that you run the ADC

above the minimum rate, and decimate. If oversampling

low frequencies, the use of a sinusoid is potentially accept-

able, but it must be very clean or the low dV/dt will result

in a great sensitivity to wideband noise in the clock driver.

The use of a divider may require a bandpass filter prior to

the divider in order to achieve best SNR as the divider can

exaggerate phase noise if it is sensitive to GHz frequen-

cies. Contact Linear Technology for recommendations or

in some cases, available clock sources or dividers.

Most generators require filtering or they will compromise

both the SNR and the SFDR of the ADCs.

Generally data sheet FFT plots are taken with 10 pole LC

filters made by TTE (Los Angeles, CA) to suppress signal

generator harmonics, non-harmonically related spurs

and broad band noise. Low phase noise Agilent 8644B

generators are used with TTE band pass filters for both

the Clock input and the Analog input. In the case of the

LTC2203/LTC2202/LTC2201 we use a divide by 4.

This demo board is, populated by default for the DC input

path. There is a transformer mounted at T1, but C4, C6,

R9 and R13 are not populated. If a single-ended AC input

is required, the DC input paths must be disconnected by

removing R26, 27, 31 and 32, and the above components

installed.

P1-P3 P4-P6 P7-P8

DC919A-I

Mfr. #:

Buy DC919A-I

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2205-14 - CMOS OUT, DC INPUT, 65Msps

Lifecycle:

New from this manufacturer.

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DC919A-I

DC919A-I

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