MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
______________________________________________________________________________________ 11
Topologies
The MAX9206/MAX9208 deserializers can operate in a
variety of topologies. Examples of double-terminated
point-to-point and point-to-point broadcast are shown
in Figures 10 and 11. Use 1% surface-mount termina-
tion resistors.
A point-to-point interface terminated at each end in the
characteristic impedance of the cable or PCB traces is
shown in Figure 10. The total load seen by the serializer
is 50Ω. The double termination typically reduces reflec-
tions compared to a single 100Ω termination. A single
100Ω termination at the deserializer input is feasible
and makes the differential signal swing larger.
A point-to-point version of a multidrop bus is shown in
Figure 11. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to a bus, more interconnect is traded for
robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter is a component of the
total jitter seen at the deserializer input (along with
other sources of jitter), a low-jitter repeater is essential
in most high data-rate applications.
Board Layout
A four-layer PCB providing separate power, ground,
and signal layers is recommended. Keep the
LVTTL/LVCMOS inputs and outputs separated from the
BLVDS inputs to prevent coupling into the BLVDS lines.
Chip Information
PROCESS: CMOS
input status.
Pin Configuration
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 SSOP A28+4
21-0056 90-0095
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
