EVAL-ADG5209FEBZ

UG-875 EVAL-ADG5209FEBZ User Guide
Rev. A | Page 4 of 12
EVALUATION BOARD HARDWARE
The operation of the ADG5209F is evaluated using the EVA L-
ADG5209FEBZ. Figure 1 shows a typical evaluation setup
where only a power supply and signal generator are required.
Figure 2 shows the block diagram of the main components of
the evaluation board.
Using this evaluation board, the ADG5209F passes signals from
either the source or drain connectors. The source pins have fault
detection circuitry that react to an overvoltage event. During an
overvoltage event, the channel on which the fault occurs is
turned off. See the ADG5209F data sheet for more details.
POWER SUPPLY
Connector J5 provides access to the supply pins of the ADG5209F.
VDD, GND, and VSS on J5 link to the appropriate pins on the
ADG5209F. For dual-supply voltages, the evaluation board can
be powered from ±5 V to ±22 V. For single-supply voltages, the
GND and VSS terminals must be connected together, and power
the evaluation board with 8 V to 44 V. Additionally, an on-board
LDO regulator is provided for a digital control voltage. If
necessary, a secondary voltage source can be connected to
EXT_VL and used to control the digital voltages. To use
EXT_VL, move the 0 resistor from R14 to R13. Do not
expose the on-board LDO regulator to voltages greater than
28 V; remove R15 and supply an alternative digital voltage via
EXT_VL, if required.
INPUT SIGNALS
Four screw connectors are provided to connect to both the
source and drain pins of the ADG5209F. Additional Subminiature
Version B (SMB) connector pads are available if extra connections
are required. The ADG5209F is overvoltage protected on the
source side, and each source terminal (S1A to S4A and S1B to
S4B) can be presented with a voltage of up to +55 V or −55 V.
See the ADG5209F data sheet for more details.
Each trace on the source and drain side includes two sets of 0603
pads that can be used to place a load on the signal path to ground.
A 0 Ω resistor is placed in the signal path and can be replaced
with a user defined value. Use the resistor combined with the
0603 pads to create a simple resistor capacitor (RC) filter.
The ADG5209F uses a parallel interface to control the operation of
the switches. The switch operation can be manually controlled
using the SW1 to SW3 switches, or an external controller can be
interfaced directly to the control pins by using the SMB connectors
(EN, A0, and A1) and removing the 0 R31, R33, and R35
resistors.
EVAL-ADG5209FEBZ User Guide UG-875
Rev. A | Page 5 of 12
JUMPER SETTINGS
SWITCHES AND 0 Ω RESISTORS
Switches control the ADG5209F manually and 0 Ω resistors
configure the digital control voltage. Table 2 shows a summary
of the switches and 0 Ω resistors and how they are used on the
evaluation board.
Use SW2 and SW3 to control the switches of the ADG5209F.
Position L (low) is tied to GND and sets the logic low, and
Position H (high) is tied to VL and sets the logic high.
Use SW1 to enable or disable the device. Position DIS (disable)
is tied to GND and disables the device, and Position EN (enable) is
tied to VL and enables the device.
Table 1. ADG5209F Truth Table
SW3 (A1) SW2 (A0) SW1 (EN) Connected Sx
X
1
X
1
DIS (disable) All switches off
L (low) L (low) EN (enable) S1A/S1B
L (low) H (high) EN (enable) S2A/S2B
H (high) L (low) EN (enable) S3A/S3B
H (high) H (high) EN (enable) S4A/S4B
1
X means don’t care.
R15 connects the on-board LDO regulator to the VDD supply.
Remove this resistor to protect the LDO regulator from voltages
higher than 28 V. Change the 0 resistor to the R13 position to
use an alternative digital voltage connected to DC_V1.
SMB CONNECTORS
The parallel interface of the ADG5209F is controlled manually
using the link headers (SW1 to SW3), or it can be accessed using
the SMB connectors (EN, A0, and A1). To us e the SMB
connectors, remove the 0 R31, R33, and R35 resistors.
Table 2. Switch and 0 Ω Resistor Descriptions
Label Position Description
SW1 DIS (disable) Logic 0 on the EN pin
EN (enable) Logic 1 on the EN pin
SW2 L (low) Logic 0 on the A0 pin
H (high) Logic 1 on the A0 pin
SW3 L (low) Logic 0 on the A1 pin
H (high) Logic 1 on the A1 pin
R13/R14 R14 On-board LDO regulator digital voltage
R13 EXT_VL digital voltage
R15 Inserted LDO regulator powered up
Removed LDO regulator unpowered
R31, R33, R35 Inserted SW1 to SW3 are used to control digital logic
Removed SMB connectors are used to control digital logic
UG-875 EVAL-ADG5209FEBZ User Guide
Rev. A | Page 6 of 12
EVALUATION BOARD SCHEMATICS AND ARTWORK
13457-008
Figure 3. ADG5209F Evaluation Board Schematic (Part 1)

EVAL-ADG5209FEBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ADG5209 Analog Switch Multiplexer Evaluation Board
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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