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CS51022ADBG

P1-P3P4-P6P7-P9P10-P11
CS51021A, CS51022A, CS51023A, CS51024A
http://onsemi.com
7
CIRCUIT DESCRIPTION
SYNC
R
T
C
T
SLOP
E
IS
V
DS
0 V
0 V
0 V
0 V
0 V
V
IN
0 V
V
COMP
PWM COMP
GATE
4.3 V
200 ns
T
CH
T
DIS
V
SLOPE
55 ns
Blanking
IS + 0.1 SLOPE
IS
Figure 3. Typical Waveforms
THEORY OF OPERATION
Powering the IC
The IC has two supply and two ground pins. V
C
and
PGND pins provide high speed power drive for the external
power switch. V
CC
and LGND pins power the control
portion of the IC. The internal logic monitors the supply
voltage, V
CC
. During abnormal operating conditions, the
output is held low. The CS51021A/2A/3A/4A requires only
75 mA of startup current.
Voltage Feedback
The output voltage is monitored via the V
FB
pin and is
compared with the internal 2.5 V reference. The error
amplifier output minus one diode drop is divided by 3 and
connected to the negative input of the PWM comparator.
The positive input of the PWM comparator is connected to
the modified current sense signal. The oscillator turns the
external power switch on at the beginning of each cycle.
When current sense ramp voltage exceeds the reference side
of PWM comparator, the output stage latches off. It is turned
on again at the beginning of the next oscillator cycle.
Current Sense and Protection
The current is monitored at the I
SENSE
pin. The
CS51021A/2A/3A/4A has leading edge blanking circuitry
that ignores the first 55 ns of each switching period.
Blanking is disabled when V
FB
is less than 2.0 V so that the
minimum on−time of the controller does not have an
additional 55 ns of delay time during fault conditions. For
the remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope
compensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided by
three error amplifier output voltage. The pulse−by−pulse
overcurrent protection threshold is set by the voltage at the
I
SET
pin. This voltage is passed through the I
SET
Clamp and
appears at the non−inverting input of the PWM comparator,
limiting its dynamic range according to the following
formula:
Overcurrent Threshold +
0.8 V
I(SENSE)
) 0.1 V ) 0.1 V
SLOPE
where
V
I(SENSE)
is voltage at the I
SENSE
pin.
and
V
SLOPE
is voltage at the SLOPE pin.
During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop
propagation delay, the sensed signal will overshoot the
pulse−by−pulse threshold eventually reaching the second
overcurrent protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
2nd Threshold + 1.33 V
I(SET)
Exceeding the second threshold will reset the Soft Start
capacitor C
SS
and reinitiate the Soft Start sequence,
repeating for as long as the fault condition persists.
Soft Start
During power up, when the output filter capacitor is
discharged and the output voltage is low, the voltage across
the Soft Start capacitor (V
SS
) controls the duty cycle. An
internal current source of 55 mA charges C
SS
. The maximum
error amplifier output voltage is clamped by the SS Clamp.
When the Soft Start capacitor voltage exceeds the error
amplifier output voltage, the feedback loop takes over the
duty cycle control. The Soft Start time can be estimated with
the following formula:
t
SS
+ 9 10
4
C
SS
The Soft Start voltage, V
SS
, charges and discharges
between 0.25 V and 4.7 V.
CS51021A, CS51022A, CS51023A, CS51024A
http://onsemi.com
8
Slope Compensation
DC−DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
C
S
is charged by an internal 53 mA current source and is
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, V
I(SENSE)
. The signal applied to the
input of the PWM comparator is a combination of these two
voltages. The slope compensation, dV
SLOPE
/dt
,
is
calculated using the following formula:
dV
SLOPE
dt
+ 0.1
53 mA
C
S
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance C
S
. This error is typically small for large values
of C
S
, but increases as C
S
becomes small and comparable to
the internal capacitance. The effect is apparent as a reduction
in charging current due to the need to charge the internal
capacitance in parallel with C
S
.Figure 4 shows a typical
curve indicating this decrease in available charging current.
Figure 4. The Slope Compensation Pin Charge
Current Reduces When a Small Capacitor Is Used.
10 100 1000
60
55
50
45
40
35
30
25
20
Charging Current (mA)
Compensation Cap (pF)
Undervoltage (UV) and Overvoltage (OV) Monitor
Two independent comparators monitor OV and UV
conditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 5). When voltage at the OV pin
exceeds 2.5 V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5 mA current source turns
on and feeds current into the external resistor, R
3
, creating
a hysteresis determined by the value of this resistor (the
higher the value, the greater the hysteresis). The hysteresis
voltage of the OV monitor is determined by the following
formula:
V
OV(HYST)
+ 12.5 mA R
3
where R
3
is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV
hysteresis.
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault
condition is detected the controller goes through the power
up sequence.
Figure 5. UV/OV Monitor Divider
V
IN
V
UV
V
OV
R
1
R
2
R
3
To calculate the OV?UV resistor divider :
1. Solve for R
3
, based on OV hysteresis requirements.
R
3
+
V
OV(HYST)
2.5 V
V
MAX
12.5 mA
where V
OV(HYST)
is the desired amount of
overvoltage hysteresis, and V
MAX
is the input voltage
at which the supply will shut down.
2. Find the total impedance of the divider.
R
TOT
+ R
1
) R
2
) R
3
+
V
MAX
R
3
2.5
3. Determine the value of R
2
from the UV threshold
conditions.
R
2
+
1.45 R
TOT
V
MIN
* R
3
where V
MIN
is the UV voltage at which the supply
will shut down.
4. Calculate R
1
.
R
1
+ R
TOT
* R
2
* R
3
5. The undervoltage hysteresis is given by :
V
UV(HYST)
+
V
MIN
0.075
1.45
V
REF
Monitor
The 5.0 V reference voltage is internally monitored to
ensure that it remains within specifications. The monitor,
which outputs a fault, can be tripped by two methods:
• If the reference voltage drops below 4.75 V
• If V
CC
falls below the STOP threshold
As indicated in the block diagram, any fault causes the
output to stop switching and begins the discharge of the Soft
Start capacitor C
SS
.
CS51021A, CS51022A, CS51023A, CS51024A
http://onsemi.com
9
Synchronization
A bi−directional synchronization is provided to synchronize
several controllers. When SYNC pins are connected together,
the converters will lock to the highest switching frequency. The
fastest controller becomes the master, producing a 4.3 V, 200
ns pulse train. Only one, the highest frequency SYNC signal,
will appear on the SYNC line.
Sleep
The sleep input is an active high input. The CS51022A/4A
is placed in sleep mode when SLEEP is driven high. In sleep
mode, the controller and MOSFET are turned off. Connect
to GND for normal operation. The sleep mode operates at
VCC ≤ 15 V.
Oscillator and Duty Cycle Limit
The switching frequency is set by R
T
and C
T
connected to
the R
T
C
T
pin. C
T
charges and discharges between 3.0 V and
1.5 V.
The maximum duty cycle is set by the ratio of the on time,
t
ON
, and the whole period, T = t
ON
+ t
OFF
. Because the timing
capacitor’s discharge current is trimmed, the maximum duty
cycle is well defined. It is determined by the ratio between the
timing resistor R
T
and the timing capacitor C
T
. Refer to figures
6 and 7 to select appropriate values for R
T
and C
T
.
f
SW
+
1
T
SW
;T
SW
+ t
CH
) t
DIS
5
2500
Frequency (kHz)
R
T
(kW)
2000
1500
1000
500
0
100
90
80
70
60
50
40
10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 5
5
R
T
(kW)
Duty Cycle (%)
1
2
3
4
5
6
8 7
2
1
3
4
8
7
5
6
1. C
T
= 47 pF
2. C
T
= 100 pF
3. C
T
= 150 pF
4. C
T
= 220 pF
5. C
T
= 390 pF
6. C
T
= 470 pF
7. C
T
= 560 pF
8. C
T
= 680 pF
1. C
T
= 47 pF
2. C
T
= 100 pF
3. C
T
= 150 pF
4. C
T
= 220 pF
5. C
T
= 390 pF
6. C
T
= 470 pF
7. C
T
= 560 pF
8. C
T
= 680 pF
Figure 6. Frequency vs. R
T
for Discrete
Capacitor Values
Figure 7. Duty Cycle vs. R
T
for Discrete
Capacitor Values
ORDERING INFORMATION
Device Package Shipping
†
CS51021AED16
SOIC−16
48 Units / Rail
CS51021AEDR16
2500 Tape & Reel
CS51021AEDR16G SOIC−16
(Pb−Free)
CS51022ADBG TSSOP−16* 48 Units / Rail
CS51022ADBR2G TSSOP−16* 2500 Tape & Reel
CS51022AED16
SOIC−16
48 Units / Rail
CS51022AEDR16
2500 Tape & Reel
CS51022AEDR16G SOIC−16
(Pb−Free)
CS51023AED16
SOIC−16
48 Units / Rail
CS51023AEDR16
2500 Tape & Reel
CS51023AEDR16G SOIC−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
P1-P3P4-P6P7-P9P10-P11

CS51022ADBG

Mfr. #:
Buy CS51022ADBG
Manufacturer:
ON Semiconductor
Description:
Switching Controllers ANA ENHANCED PWM CTRL
Lifecycle:
New from this manufacturer.
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