IPM6220ACAZ Datasheet IPM6220ACAZA-T, IPM6220ACAZ, IPM6220ACAZ-T | P4-P6

Absolute Maximum Ratings Thermal Information

Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V

Phase, ISEN and SDWNALL

Pins. . . . . . . . . . . GND -0.3V to +27.0V

Boot and UGATE Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0V

BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V

Operating Conditions

Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +24.0V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-10°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C

Thermal Resistance (Typical, Note 1) 

(°C/W)

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SSOP - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. 

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Input Quiescent Current I

SDWN1 = SDWN2 = 5V, SDWNALL = VIN,

Outputs open circuited

-1.42.0mA

Stand-by Current I

CCSB

SDWN1 = SDWN2 = 0V, SDWNALL = VIN,

Outputs open circuited

- 300 A

Shut-down Current I

CCSN

SDWNALL = 0V - <1.0 A

Input Under-voltage Lock Out UVLO Rising VBATT 4.3 4.7 5.1 V

Input Under-voltage Lock Out UVLO VBATT, Hysteresis 300 mV

OSCILLATOR

PWM1,2 Oscillator Frequency F

c1,2

255 300 345 kHz

REFERENCE AND SOFT START

Internal Reference Voltage V

REF

- 2.472 - V

Reference Voltage Accuracy -1.0 - +1.0 %

SDWN1, SDWN2 Output Current During

Start-up

-5- A

PWM1 CONVERTER, 5V Main

Output Voltage V

OUT1

5.0V

Line and Load Regulation 0.0 < IVOUT1 < 5.0A; 5.6V < VBATT < 22.0V -2 0.5 +2 %

Under-Voltage Shut-Down Level V

UV1

2s delay, % Feedback Voltage at VSNS1 pin 70 75 80 %

Current Limit Threshold I

OC2

Current from ISNS1 Pin Through RSNS1 90 135 180 A

Over-Voltage Threshold V

OVP1

2s delay, % Feedback Voltage at VSNS1 pin 110 115 120 %

Maximum Duty Cycle DC

MAX

SDWN1 > 4.0V 94 %

PWM2 CONVERTER, 3.3V Main

Output Voltage VOUT2 3.3 V

Line and Load Regulation 0.0 < IVOUT2 < 5.0A; 5.6V < VBATT < 24.0V -2 0.5 +2 %

Under-Voltage Shut-Down Level V

UV2

2s delay, % Feedback Voltage at VSNS2 pin 70 75 80 %

Current Limit Threshold I

OC2

Current from ISNS2 Pin Through RSNS2 90 135 180 A

Over-Voltage Threshold V

OVP2

2s delay, % Feedback Voltage at VSNS2 pin 110 115 120 %

Maximum Duty Cycle DC

MAX

SDWN2 > 4.0V 94 %

Internal Resistance to GND on VSNS2 Pin R

VSNS2

66K 

IPM6220A

PWM1 and PWM2 CONTROLLER GATE DRIVERS

Upper Drive Pull-Up Resistance R

2UGPUP

-512 

Upper Drive Pull-Down Resistance R

2UGPDN

-410 

Lower Drive Pull-Up Resistance R

2LGPUP

-69 

Lower Drive Pull-Down Resistance R

2LGPDN

-58 

PWM 3 CONVERTER

12V Feedback Regulation Voltage VSEN3 2.472 V

12V Feedback Regulation Voltage Input

Current

VSEN3

0.1 1.0 A

Line and Load Regulation 0.0 < IV

OUT3

< 120mA, 4.9V< 5V

Main

<5.1V -2 +2 %

Under-Voltage Shut-Down Level V

UV3

2s delay, % Feedback Voltage at VSNS3 pin 70 75 80 %

Over-Voltage Threshold V

OVP3

2s delay, % Feedback Voltage at VSNS3 pin 115 120 %

PWM3 Oscillator Frequency F

85 100 115 kHz

Maximum Duty Cycle 33 %

PWM 3 CONTROLLER GATE DRIVERS

Pull-Up Resistance R3GPUP 6 12 

Pull-Down Resistance R3GPDN 6 12 

5V and 3.3V ALWAYS

Linear Regulator Accuracy PWM1, 5V Output OFF (SDWN1

= 0V);

5.6V < VBATT < 22V; 0 < I

LOAD

< 50mA

-2.0 0.5 +2.0 %

5V ALWAYS Output Voltage Regulation PWM1, 5V Output ON (SDWN1

= 5V);

0 < I

LOAD

< 50mA

-3.3 1.0 +2.0 %

Maximum Output Current Combined 5V ALWAYS and 3.3V ALWAYS 50 mA

Current Limit Combined 5V ALWAYS and 3.3V ALWAYS 100 180 mA

5V ALWAYS Under-Voltage Shut-Down 75 %

Bypass Switch r

DS(ON)

PWM1, 5V Output ON (SDWN1 = 5V) 1.3 

POWER GOOD AND CONTROL FUNCTIONS

Power Good Threshold for PWM1 and

PWM2 Output Voltages

-14 -12 -10 %

PGOOD Leakage Current I

PGLKG

VPULLUP = 5.0V - - 1.0 A

PGOOD Voltage Low V

PGOOD

= -4mA 0.2 0.5 V

PGOOD Minimum Pulse Width T

PGmin

10 s

SDWN1, 2

, - Low (Off) 0.8 V

SDWN1, 2

, - High (On) 4.3 V

SDWNALL

- High (On) 2.4 V

SDWNALL

- Low (Off) SDWNALL, Hysteresis 40 mV

Over-Temperature Shutdown 150 °C

Over-Temperature Hysteresis 25 °C

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

IPM6220A

Functional Pin Descriptions

VBATT (Pin 1)

Supplies all the power necessary to operate the chip. The IC

starts to operate when the voltage on this pin exceeds 4.7V

and stops operating when the voltage on this pin drops

below approximately 4.5V. Also provides battery voltage to

the oscillator for feed-forward rejection to input voltage

variations.

3.3V ALWAYS (Pin 2)

Output of 3.3V ALWAYS linear regulator.

5V ALWAYS (Pin 6)

Output of 5V ALWAYS linear regulator or the +5V Main

output. If the +5V Main output is enabled, it is switched

internally from the VSEN1 pin to the 5V ALWAYS output.

This improves efficiency and reduces the power dissipation

in the controller.

BOOT1, BOOT2 (Pins 24 and 3)

Power is supplied to the upper MOSFET drivers of PWM1

and PWM2 converters via the BOOT pins. Connect these

pins to the respective junctions of bootstrap capacitors with

the cathodes of the bootstrap diodes. Anodes of the

bootstrap diodes are connected to pin 6, 5V ALWAYS.

UGATE1, UGATE2 (Pins 23 and 4)

These pins provide the gate drive for the upper MOSFETs.

Connect UGATE pins to the respective PWM converter’s

upper MOSFET gate.

PHASE1, PHASE2 (Pins 22 and 5)

The phase nodes are the junctions of the upper MOSFET

sources, output filter inductors, and lower MOSFET drains.

Connect the PHASE pins directly to the respective PWM

converter’s lower MOSFET drain.

ISEN1, ISEN2 (Pins 21 and 9)

These pins are used to monitor the voltage drop across the

lower MOSFETs for current feedback and current-limit

protection. For more precise current detection, these inputs

can be connected to optional current sense resistors placed

in series with the sources of the lower MOSFETs.

LGATE1, LGATE 2 (Pins 20 and 7)

These pins provide the gate drive for the lower MOSFETs.

Connect the lower MOSFET gate of each converter to the

corresponding pin.

PGND1, PGND2 (Pins 19 and 8)

These are the lower MOSFET gate drive return connection

for PWM1 and PWM2 converters, respectively. Tie each

lower MOSFET source directly to the corresponding pin.

VSEN1, VSEN2 (Pins 18, 10)

These pins are connected to the main outputs and provide

the voltage feedback signal for the respective PWM

controllers. The PGOOD, overvoltage protection (OVP) and

undervoltage shutdown circuits use these signals to

determine output-voltage status and/or to initiate

undervoltage shut down. The VSEN1 input is also switched

internally to the 5V ALWAYS output if the +5V Main output is

enabled.

SDWNALL (Pin 13)

This pin provides enable/disable function for all outputs. The

chip is completely disabled when this pin is pulled to ground.

When this pin is pulled high, the 5V ALWAYS and 3.3

ALWAYS outputs are on and the other outputs are enabled.

The state of 5V Main and 3.3V Main outputs depend on the

voltage on SDWN1

and SDWN2 respectively. See Table 1.

SDWN1 (Pin 17)

This pin provides enable/disable function and soft-start for

the PWM1, 5V Main, output. The output is enabled when this

pin is high and SDWNALL

is also high. The 5V output is held

off when the pin is pulled to the ground.

SDWN2 (Pin 11)

This pin provides enable/disable function and soft-start for

PWM2, 3.3V Main, output. The output is enabled when this

pin is high and SDWNALL

is also high. The 3.3V output is

held off when the pin is pulled to the ground.

VSEN3 (Pin 15)

This input pin is the voltage feedback signal for PWM3, the

boost controller. The boost controller regulates this point to a

voltage divided level of 2.472 VDC. The PGOOD,

overvoltage protection (OVP) and undervoltage shutdown

circuits use this signal to determine output-voltage status

and/or to initiate undervoltage shut down.

This pin can also be used to independently disable the

PWM3 controller. Connect this pin to 5V ALWAYS if the

boost converter is not populated in your design.

GATE3 (Pin 16)

This pin drives the gate of the boost MOSFET.

PGOOD (Pin 12)

PGOOD is an open drain output used to indicate the status

of the PWM converters’ output voltages. This pin is pulled

low when any of the outputs except PWM3 (12V) is not

within -10% of respective nominal voltages, or when PWM3

(12V) is not within its undervoltage and overvoltage

thresholds.

GND (Pin 14)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

General Description

The IPM6220A addresses the system electronics power

needs of modern notebook and sub-notebook PCs. The IC

integrates control circuits for two synchronous buck

IPM6220A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

IPM6220ACAZ

Mfr. #:

Buy IPM6220ACAZ

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers 30V CS80 FSC PROCESS W/IMPROVED ESD STRUC

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IPM6220ACAZ

IPM6220ACAZ

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