Pre-Production WM7211
w
PP, Rev 3.1, January 2014
7
AUDIO INTERFACE TIMING
Figure 1 Digital Microphone Interface Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER SYMBOL MIN TYP MAX UNIT
Digital Microphone Interface Timing
CLK cycle time t
CY
308 1000 ns
CLK duty cycle 60:40 40:60
DAT enable from rising CLK edge (LRSEL = 1) t
L_EN
18 ns
DAT disable from falling CLK edge (LRSEL = 1) t
L_DIS
16 ns
DAT enable from falling CLK edge (LRSEL = 0) t
R_EN
18 ns
DAT disable from rising CLK edge (LRSEL = 0) t
R_DIS
16 ns
Notes:
1. The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be
connected together, with the data from one microphone interleaved with the data from the other. (The microphones
must be configured to transmit on opposite channels in this case.)
2. In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the
Left channel should be sampled by the receiving device on the falling CLK edge,
3. Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right
channel should be sampled by the receiving device on the rising CLK edge.