Advanced Clock Drivers Device Data
6 Freescale Semiconductor
MPC9992
Table 7. AC Characteristics (V
CC
= 3.3 V ± 5%, GND = 0 V, T
A
= 0°C to +70°C)
(1)
1. AC characteristics apply for parallel output termination of 50 Ω to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input Reference Frequency ÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
÷160 feedback
Input Reference Frequency in PLL Bypass Mode
(2)
2. In bypass mode, the MPC9992 divides the input reference clock.
25.0
16.67
12.5
10.0
8.33
5.0
50.0
33.3
25.0
20.0
16.67
10.0
400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
f
XTAL
Crystal Interface Frequency Range
(3)
3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
f
XTAL(min, max)
= f
VCO(min, max)
÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f
XTAL
≤ 20 MHz.
10 20 MHz
f
VCO
VCO Frequency Range
(4)
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
ref
= f
VCO
÷ (M ⋅ VCO_SEL)
800 1600 MHz
f
MAX
Output Frequency ÷4 output
÷8 output
÷12 output
÷16 output
÷20 output
÷24 output
÷48 output
200.0
100.0
66.6
50.0
40.0
33.3
16.6
400.0
200.0
133.3
100.0
80.0
66.6
33.3
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
V
PP
Differential Input Voltage
(5)
(peak-to-peak)
5. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics.
0.3 1.3 V
V
CMR
Differential Input Crosspoint Voltage
(6)
(PCLK)
6. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
(AC)
range and the input swing lies within the V
PP
(AC) specification.
1.2 V
CC
–0.3 V
V
O(P-P)
Differential Output Voltage (peak-to-peak) (PCLK) 0.6 0.8 V
t
PW,MIN
Input Reference Pulse Width
(7)
7. Calculation of reference duty cycle limits: DC
REF,MIN
= t
PW,MIN
⋅ f
REF
⋅ 100% and DC
REF,MAX
= 100% – DC
REF, MIN.
E.g. at f
REF
= 50 MHz
the input duty cycle range is 10% < DC < 90%.
2.0 ns
t
sk(O)
Output-to-Output Skew 100 ps
DC Output Duty Cycle
(8)
8. Output duty cycle for QAx and QBx outputs. The pulse width for the QSYNC output is equal to one QAx output period t
QA
± 5%.
48 50 52 %
t
JIT(CC)
Cycle-to-Cycle Jitter
(9)
9. Jitter data is valid f
ref
= 25 MHz.
30 79 ps
t
JIT(PER)
Period Jitter
(9)
43 106 ps
t
JIT(∅)
I/O Phase Jitter
(9)
RMS (1 σ)
(10)
10. See application section for a jitter calculation for other confidence factors than 1 σ.
86 212 ps
BW PLL Closed Loop Bandwidth
(11)
÷32 feedback
÷48 feedback
÷64 feedback
÷80 feedback
÷96 feedback
÷160 feedback
11. –3 dB point of PLL transfer characteristics.
0.60-1.5
0.40-1.2
0.30-1.0
0.30-0.8
0.20-0.7
0.15-0.4
MHz
MHz
MHz
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time 10 ms
t
r
, t
f
Output Rise/Fall Time 0.05 1.0 ns 20% to 80%
