12/15
BD48xxx series BD49xxx series
TSZ02201-0R7R0G300030-1-
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
●Application Information
Explanation of Operation
For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
DD
pins reaches the appropriate threshold voltage, the V
OUT
terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical
Characteristics for information on hysteresis.
Because the BD48xxx series uses an open drain output type, it is necessary to connect a pull-up resistor to V
DD
or another
power supply if needed [The output “High” voltage (V
OUT
) in this case becomes V
DD
or the voltage of the other power
supply].
Fig.12 (BD48xxx series Internal Block Diagram) Fig.13 (BD49xxx series Internal Block Diagram)
Reference Data
Examples of Leading (t
PLH
) and Falling (t
PHL
) Output
Part Number t
PLH
(µs) t
PHL
(µs)
BD48x45 39.5 87.8
BD49x45 32.4 52.4
V
DD
=4.3V5.1V V
DD
=5.1V4.3V
*These data are for reference only.
The figures will vary with the application, so please check actual operating conditions before use.
Timing Waveform
Example: the following shows the relationship between the input voltages V
DD
and the output voltage V
OUT
when the
input power supply voltage V
DD
swept up and down (the circuits are those in Fig.12 and 13).
When the power supply is turned on, the output is unstable
from after over the operating limit voltage (VOPL) until tPHL.
Therefore it is possible that the reset signal is not outputted when
the rise time of V
DD
is faster than tPHL.
When V
DD
is greater than V
OPL
but less than the reset release
voltage (V
DET
+ ∆V
DET
), the output voltages will switch to Low.
If V
DD
exceeds the reset release voltage (V
DET
+ ∆V
DET
), then
V
OUT
switches from L to H.
If V
DD
drops below the detection voltage (V
DET
) when the power
supply is powered down or when there is a power supply
fluctuation, V
OUT
switches to L (with a delay of t
PHL
).
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (∆V
DET
). The
system is designed such that the output does not toggle with
power supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
V
DD
VDET+ΔVDET
VDET
VOPL
0V
tPHL
①
②
V
OUT
tPLH
tPHL
tPLH
③
④
VOL
VOH
⑤
Fig.14 Timing Waveform
R1
R2
V
DD
GND
Q1
V
OUT
R3
R
L
R1
R2
R3
Q2
Q1
V
DD
V
OUT
GND
