© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
1 Publication Order Number:
74ALVC16373/D
74ALVC16373
Low−Voltage 1.8/2.5/3.3 V
16−Bit Transparent Latch
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74ALVC16373 is an advanced performance, non−inverting
16−bit transparent latch. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
ALVC16373 is byte controlled, with each byte functioning identically,
but independently. Each byte has separate Output Enable and Latch
Enable inputs. These control pins can be tied together for full 16−bit
operation.
The 74ALVC16373 contains 16 D−type latches with 3−state
3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3−state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches.
• Designed for Low Voltage Operation: V
CC
= 1.65−3.6 V
• 3.6V Tolerant Inputs and Outputs
• High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000 V; Machine Model
>200 V
• Second Source to Industry Standard 74ALVC16373
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to V
CC
through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
MARKING DIAGRAM
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
TSSOP−48
DT SUFFIX
CASE 1201
1
48
74ALVC16373DT
AWLYYWW
1
48
Device Package Shipping
ORDERING INFORMATION
74ALVC16373DTR TSSOP 2500/Tape & Reel
PIN NAMES
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
Pins
OEn
LEn
D0−D15
O0−O15
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