MAX5432–MAX5435
32-Tap, Nonvolatile, I
2
C, Linear, Digital
Potentiometers
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V, V
H
= V
DD
, V
L
= GND, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= +5V, T
A
=
+25°C.) (Figures 1 and 2) (Note 1)
Typical Operating Characteristics
(V
DD
= +5V, T
A
= +25°C, unless otherwise noted.)
Note 2: The DNL and INL are measured with the potentiometer configured as a variable resistor. For the 3-terminal potentiometers
(MAX5432/MAX5433), H is unconnected and L = GND. At V
DD
= 5V, W is driven with a source current of 80µA for the 50kΩ
configuration, and 40µA for the 100kΩ configuration. At V
DD
= 3V, W is driven with a source current of 40µA for the 50kΩ
configuration, and 20µA for the 100kΩ configuration.
Note 3: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = V
DD
and L = GND
(MAX5432/MAX5433 only). The wiper terminal is unloaded and measured with an ideal voltmeter.
Note 4: Full-scale error is defined as
Note 5: Zero-scale error is defined as
Note 6: The wiper resistance is the worst value measured by injecting the currents given in Note 2 into W with L = GND.
R
W
= (V
W
- V
H
) / I
W
.
Note 7: The device draws current in excess of the specified supply current when the digital inputs are driven with voltages between
(V
DD
- 0.5V) and (GND + 0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
Note 8: Wiper is at midscale with a 10pF capacitive load. Potentiometer set to midscale, L = GND, an AC source is applied to H,
and the output is measured as 3dB lower than the DC W/H value in dB.
Note 9: This is measured from the STOP pulse to the time it takes the output to reach 50% of the output step size (divider mode). It
is measured with a maximum external capacitive load of 10pF.
Note 10: The programming current exists only during NV writes (12ms typ).
Note 11: Digital timing is guaranteed by design and characterization, and is not production tested.
Note 12: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the I
2
C-bus specifica-
tion document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf
Note 13: The idle time begins from the initiation of the stop pulse.
