MAX7490/MAX7491
Dual Universal Switched-Capacitor Filters
______________________________________________________________________________________ 13
Mode 3
Figure 6 shows the configuration of Mode 3. This mode
is a sampled time (Z transform) equivalent of the classi-
cal 2nd-order state variable filter. In this versatile mode,
the ratio of resistors R2 and R4 can move the center
frequency both above and below the nominal ratio.
Mode 3 is commonly used to make multiple-pole
Chebyshev filters with a single clock frequency. This
mode can also be used to make high-order all-pole
bandpass, lowpass, and highpass filters.
Mode 3 Design Equations
Mode 3A
Figure 7 shows the configuration of Mode 3A. Similar to
Mode 2, this mode adds an external op amp. See
Table 3 for op amp selection ideas. This op amp cre-
ates a highpass notch and lowpass notch by summing
the highpass and lowpass outputs through two external
resistors, R
H
and R
L
. The ratio of resistors R
H
and R
L
adjusts the notch frequency, while R2 and R4 adjust
the bandpass center frequency, since the notch (zero
pair) frequency can be adjusted to both above and
below f
O
. Mode 3A is suitable for both lowpass and
highpass elliptic or Cauer filters. In multipole elliptic fil-
ters, only one external op amp is needed. Use the
inverting input of the internal op amp as the summing
node for all but the final section of the filter.
f
O
f
CLK
R
R
Q
R
R
R
R
H
OHP
R
R
H
OLP
R
R
H
OBP
R
R
=
=
=
=
=
100
2
4
3
2
2
4
2
1
4
1
3
1
Σ
LP
BPHP
R3
R4
R2
R1
V
IN
C
C
COM
+
-
S
COM
Figure 6. Mode 3, 2nd-Order Section Providing Highpass,
Bandpass, and Lowpass Outputs
Σ
LPBPN/HP
R3
R4
R2
R1
V
IN
C
C
COM
COM
LOWPASS
NOTCH
OUTPUT
+
-
R
H
R
L
R
G
S
COM
Figure 7. Mode 3A, 2nd-Order Filter Providing Highpass Notch or Lowpass Notch Outputs
MAX7490/MAX7491
Dual Universal Switched-Capacitor Filters
14 ______________________________________________________________________________________
Mode 3A Design Equations
Note: When the passband gain error exceeds 1dB, the
use of capacitor C
C
between the lowpass output and
the inverting input will reduce the gain error. The value
can best be determined experimentally. Typically, it
should be about 5pF/dB (C
C-MAX
= 15pF).
Offset Voltage
Switched-capacitor integrators generally exhibit higher
input offsets than discrete RC integrators. The larger
offset is mainly due to the charge injection of the CMOS
switches into the integrating capacitors. The internal op
amp offset also adds to the overall offset value. Figure
8 shows the input offsets from a single 2nd-order sec-
tion. Table 4 lists the formula for the output offset volt-
age for various modes and output pins.
Power Supplies
The MAX7490 operates from a single +5V supply, and
the MAX7491 operates from a single +3V supply.
Bypass V
DD
to GND with at least a 0.1µF capacitor.
V
DD
should be isolated from other digital or high-volt-
age analog supplies. If dual supplies are required, con-
nect the COM pin to the system ground and the GND
pin to the negative supply. Figure 9 shows an example
of dual-supply operation. Single-supply and dual-sup-
ply performances are equivalent. For dual-supply oper-
ation, drive CLK, SHDN, and EXTCLK from GND (which
is now V-) to V
DD
. If using the internal oscillator in dual-
supply mode, C
OSC
can be returned to either GND or
the actual ground voltage. Use the MAX7490 for ±2.5V
and use the MAX7491 for ±1.5V.
For most applications, a 0.1µF bypass capacitor from
COM to GND is sufficient. If the V
DD
supply has signifi-
cant 60Hz energy, increase this capacitor to 1µF or
greater to provide better power-supply rejection.
f
f
R
R
f
fR
R
Q
R
R
R
R
H
R
R
H
R
R
H
R
R
HfHz
R
R
R
R
Hatff
R
R
R
R
O
CLK
n
CLK H
L
OHP
OLP
OBP
ON
G
L
ON CLK
G
H
=
=
=
=
=
=
→=
==
100
2
4
100
3
2
2
4
2
1
4
1
3
1
0
4
1
2
2
1
1
2
()
(/)
Figure 8. Block Diagram of a 2nd-Order Section Showing the Input Offsets
Σ
N/HP
S
INV
BP LP
COM
V
OS1
V
OS2
V
OS3
+
-
PART GBW (MHz) SLEW RATE (V/μs) I
SUPPLY/AMP
(mA) PIN-PACKAGE
MAX4281 2 0.7 0.5 5 SOT23
MAX4322 5 2.0 1.1 5 SOT23
MAX4130 10 4.0 1.15 5 SOT23
MAX4490 10 10.0 2.0 5 SOT23
Table 3. Suggested External Op Amps
MAX7490/MAX7491
Dual Universal Switched-Capacitor Filters
______________________________________________________________________________________ 15
Input Signal Amplitude Range
The optimal input signal range is determined by
observing the voltage level at which the signal-to-noise
plus distortion (SINAD) ratio is maximized for a given
corner frequency. The
Typical Operating Character-
istics
show the THD + Noise response as the input sig-
nal’s peak-to-peak amplitude is varied. In most
systems, the input signal should be kept as large as
possible to maximize the signal-to-noise ratio (SNR).
Allow sufficient headroom to ensure no signal clipping
under expected operating conditions.
Anti-Aliasing and Post-DAC Filtering
When using the MAX7490/MAX7491 for anti-aliasing or
post-DAC filtering, synchronize the DAC (or ADC) and
the filter clocks. If the clocks are not synchronized,
beat frequencies may alias into the desired passband.
Aliasing
Aliasing is an inherent phenomenon of most switched-
capacitor filters. As with all sampled systems, frequen-
cy components of the input signal above one half the
sampling rate will be aliased. The MAX7490/MAX7491
sample at twice the clock frequency, yielding a 200:1
sampling to cutoff frequency ratio.
In particular, input signal components (f
IN
) near the
sampling rate generate a difference frequency
(f
SAMPLING
- f
IN
) that often falls within the passband of
the filter. Such aliased signals, when they appear at the
output, are indistinguishable from real input informa-
tion. For example, the aliased output signal generated
when a 99kHz waveform is applied to a filter sampling
at 100kHz, (f
CLK
= 50kHz) is 1kHz. This waveform is an
attenuated version of the output that would result from
a true 1kHz input. Since sampling is done at twice the
clock frequency, the Nyquist frequency is the same as
the clock frequency.
A simple passive RC lowpass input filter is usually suffi-
cient to remove input frequencies that can be aliased.
In many cases, the input signal itself may be band limit-
ed and require no special anti-alias filtering. Selecting
a passive filter cutoff frequency equal to f
C
/2 gives
12dB rejection at the Nyquist frequency.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the
clock frequency and its harmonics that are present at
the filter’s output pins, even without input signal. The
clock feedthrough can be greatly reduced by adding a
simple RC lowpass network at the final filter output.
Choose a cutoff frequency as low as possible to pro-
vide maximum noise attenuation. The attenuation and
phase shift of the external filter will limit the actual fre-
quency selected.
V
DD
V+
V-
CLK
GND
0.1μF
CLOCK
*DRIVE SHDN TO V- FOR LOW-POWER
SHUTDOWN MODE.
SHDN
COM
0.1μF
MAX7490
MAX7491
*
V+
V-
Figure 9. Dual-Supply Operation
MODE V
OSN/HP
V
OSBP
V
OSLP
1
V
OS1
[1 + (R2 / R3) + (R2 / R1)] - (V
OS3
)
(R2 / R3)
V
OS3
V
OSN/HP
- V
OS2
1b
V
OS1
[1 + (R2 / R3) + (R2 / R1)] - (V
OS3
)
(R2 / R3)
V
OS3
(V
OSN/HP
- V
OS2
)[1 + R5 / R6)]
2
V
OS1
[1 + (R2 / R3) + (R2 / R1) + (R2 / R4) -
(V
OS3
)(R2 / R3)][R4 / R2 + R4] +
(V
OS2
)[R2 / R2 + R4]
V
OS3
V
OSN/HP
- V
OS2
3V
OS2
V
OS3
V
OS1
[1 + (R4 / R1) + (R4 / R2) + (R4 / R3)] - (V
OS2
)
(R4 / R2) - (V
OS3
)(R4 / R3)
Table 4. Output DC Offsets for a 2nd-Order Section

MAX7490EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Active Filter Dual Universal Switched-Cap
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