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NCP1079BAP130G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
www.onsemi.com
28
design, we have selected our maximum voltage
around 650 V (at
V
IN
= 375 V dc). This voltage is
given by the RCD clamp installed from the drain to
the bulk voltage. We will see how to calculate it later
on.
4. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
D
MAX
+
N @
ǒ
V
OUT
) V
F
Ǔ
N @
ǒ
V
OUT
) V
F
Ǔ
) V
IN,MIN
+
(eq. 8)
1
1 )
V
IN,MIN
N@(V
OUT
)V
F
)
+ 0.44
5. To obtain the primary inductance, we have the
choice between two equations:
L +
ǒ
V
IN
@ D
Ǔ
2
f
SW
@ K @ P
IN
(eq. 9)
K +
DI
L
I
Lavg
(eq. 10)
where
and defines the amount of ripple we want in CCM,
depicted by Figure 51.
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
• Large K: approaching DCM where the conduction
losses are worse, but smaller inductance, leading to a
better leakage inductance.
From Equation 9, a K factor of 1 (50% ripple), gives an inductance of:
DI
L
+
V
IN
@ D
L @ f
SW
+
127 @ 0.44
3.8 @ 10
−3
@ 65 @ 10
3
+ 223 mA
(eq. 11)
L +
(
127 @ 0.44
)
2
65 k @ 1 @ 12.75
+ 3.8 mH
peak−to−peak
The peak current can be evaluated to be:
I
PEAK
+
I
avg
D
)
DI
L
2
+
98 @ 10
−3
0.44
)
223 @ 10
−3
2
+ 335 mA
(eq. 12)
On I
L
, I
Lavg
can also be calculated
I
Lavg
+ I
PEAK
*
DI
L
2
+ 335 @ 10
−3
*
223 @ 10
−3
2
+ 223 mA
(eq. 13)
6. Based on the above numbers, we can now evaluate the conduction losses:
I
D,RMS
+ D
ǒ
I
PEAK
2
* I
PEAK
@ DI
L
)
DI
L
2
3
Ǔ
Ǹ
+ 0.44
ǒ
0.335
2
* 0.335 @ 0.223 )
0.223
2
3
Ǔ
Ǹ
+ 154 mA
(eq. 14)
If we take the maximum R
DS(ON)
for a 125°C junction temperature, i.e. 10.1 W, then conduction losses worse case are:
P
COND
+ I
D,RMS
2
@ R
DS(ON)
+
ǒ
154 @ 10
−3
Ǔ
2
@ 13.6 + 323 mW
(eq. 15)
7. Off−time and on−time switching losses can be estimated based on the following calculations:
P
OFF
+
I
PEAK
@ (V
BULK
) V
CLAMP
) @ t
F
2 @ T
SW
+
0.335 @ (127 ) 120 @ 2) @ 10 @ 10
−9
2 @ 15.4 @ 10
−6
+ 40 mW
(eq. 16)
Where, assume the V
CLAMP
is equal to 2 times of reflected voltage.
P
ON
+
I
VALLEY
@
ǒ
V
BULK
) N @ (V
OUT
) V
F
)
Ǔ
@ t
R
6 @ T
SW
+
0.112 @ (127 ) 100) @ 20 @ 10
−9
6 @ 15.4 @ 10
−6
+ 5.5 mW
(eq. 17)
It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the
snubber and parasitic capacitance seen from drain pin. Therefore the t
F
and t
R
in Equations 16 and 17 have to be modified after
measuring on the bench.
8. The theoretical total power is then
P
MOSFET
+ 323 ) 40 ) 5.5 + 368.5 mW
9. If the NCP107xu operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this
device on the following calculation:
P
DSS
+ I
CC1
@ V
IN,MAX
+ 1.5 @ 10
−3
@ 375 + 563 mW
(eq. 18)
NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
www.onsemi.com
29
MOSFET Protection
As in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BV
DSS
which
is 700 V. Figure 52 a−b−c present possible implementations:
Figure 52. Different Options to Clamp the Leakage Spike
Figure 52a: the simple capacitor limits the voltage
according to the lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of a large
leakage inductance) or in normal operation as shown by
Figure 50. This condition sets the maximum voltage that can
be reflected during t
F
. As a result, the flyback voltage which
is reflected on the drain at the switch opening cannot be
larger than the input voltage. When selecting components,
you must adopt a turn ratio which adheres to the following
Equation 6. This option is only valid for low power
applications, e.g. below 5 W, otherwise chances exist to
destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with (Equation 7). Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses...
Figure 52b: the most standard circuitry is called the RCD
network. You calculate
R
CLAMP
and C
CLAMP
using the
following formulae:
R
CLAMP
+
2 @ V
CLAMP
ǒ
V
CLAMP
) (V
OUT
) V
F
) @ N
Ǔ
L
LEAK
@ I
LEAK
2
@ f
SW
(eq. 19)
C
CLAMP
+
V
CLAMP
V
RIPPLE
@ f
SW
@ R
CLAMP
(eq. 20)
V
CLAMP
is usually selected 50−80 V above the reflected
value
N x (V
OUT
+ V
F
). The diode needs to be a fast one
and a MUR160 represents a good choice. One major
drawback of the RCD network lies in its dependency upon
the peak current. Worse case occurs when
I
PEAK
and V
IN
are
maximum and
V
OUT
is close to reach the steady−state value.
Figure 52c: this option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a Zener
diode or a TVS. There are little technology differences
behind a standard Zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of Zener.
A 5 W Zener diode like the 1N5388B will accept 180 W
peak power if it lasts less than 8.3 ms. If the peak current in
the worse case (e.g. when the PWM circuit maximum
current limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5 W of continuous power
but is able to accept surges up to 600 W @ 1 ms. Select the
Zener or TVS clamping level between 40 to 80 volts above
the reflected output voltage when the supply is heavily
loaded.
As a good design practice, it is recommended to
implement one of this protection to ensure a maximum drain
pin voltage below 650 V (to have some margin between
drain pin voltage and BV
DSS
) during most stringent
operating conditions (high V
IN
and peak power condition).
NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
www.onsemi.com
30
Power Dissipation and Heatsinking
The NCP107xu welcomes two dissipating terms, the DSS
current−source (when active) and the MOSFET. Thus,
P
TOT
= P
DSS
+ P
MOSFET
. It is mandatory to properly
manage the heat generated by losses. If no precaution is
taken, risks exist to trigger the internal thermal shutdown
(TSD). To help dissipating the heat, the PCB designer must
foresee large copper areas around the package. Take the
PDIP−7 package as an example, when surrounded by a
surface approximately 200 mm
2
of 35 mm copper, the
maximum power the device can thus evacuate is:
P
MAX
+
T
J(max)
* T
AMB(max)
R
qJA
(eq. 21)
which gives around 1300 mW for an ambient of 50°C and
a maximum junction of 150°C. If the surface is not large
enough, the R
q
JA
is growing and the maximum power the
device can evacuate decreases. Figure 53 gives a possible
layout to help drop the thermal resistance.
Figure 53. A Possible PCB Arrangement to Reduce
the Thermal Resistance Junction−to−Ambient
Bill of Material:
C
1
Bulk capacitor, input dc voltage is
connected to the capacitor
C
2
, R
1
, D
1
Clamping elements
C
3
V
CC
capacitor
OK
1
Opto−coupler
ORDERING INFORMATION
Device
Frequency
[kHz]
R
DS(ON)
[W]
I
PK
[mA]
Soft−start
[ms]
Ac Line OVP
Level [V]
Package Type Shipping
NCP1075AAP065G 65 13.5 400 10 2.9 PDIP8 (Less pin#6)
50 Units /
Rail
NCP1075AAP100G 100 13.5 400 10 2.9 PDIP8 (Less pin#6)
NCP1075BAP065G 65 13.5 400 10 2.9 PDIP8 (Less pin#3)
NCP1075BAP100G 100 13.5 400 10 2.9 PDIP8 (Less pin#3)
NCP1076AAP065G 65 4.8 650 10 2.9 PDIP8 (Less pin#6)
NCP1076AAP100G 100 4.8 650 10 2.9 PDIP8 (Less pin#6)
NCP1076BAP065G 65 4.8 650 10 2.9 PDIP8 (Less pin#3)
NCP1076BAP100G 100 4.8 650 10 2.9 PDIP8 (Less pin#3)
NCP1077AAP065G 65 4.8 800 10 2.9 PDIP8 (Less pin#6)
NCP1077AAP100G 100 4.8 800 10 2.9 PDIP8 (Less pin#6)
NCP1077BAP065G 65 4.8 800 10 2.9 PDIP8 (Less pin#3)
NCP1077BAP100G 100 4.8 800 10 2.9 PDIP8 (Less pin#3)
NCP1079AAP065G 65 2.9 1050 10 2.9 PDIP8 (Less pin#6)
NCP1079AAP100G 100 2.9 1050 10 2.9 PDIP8 (Less pin#6)
NCP1079BAP065G 65 2.9 1050 10 2.9 PDIP8 (Less pin#3)
NCP1079BAP100G 100 2.9 1050 10 2.9 PDIP8 (Less pin#3)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

NCP1079BAP130G

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Manufacturer:
ON Semiconductor
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AC/DC Converters ENHANCED OFF-LINE SWITCHE
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