NTD4809N, NVD4809N
http://onsemi.com
5
TYPICAL PERFORMANCE CURVES
C
rss
10 0 10 15 25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
1000
0
V
GS
V
DS
2000
55
V
GS
= 0 VV
DS
= 0 V
T
J
= 25°C
C
iss
C
oss
C
rss
C
iss
1500
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS
0
2
0
Q
G
, TOTAL GATE CHARGE (nC)
4
105
I
D
= 30 A
0 V < V
GS
< 11.5 V
T
J
= 25°C
Q
2
Q
T
2
0
0.5
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
I
S
, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
R
G
, GATE RESISTANCE (OHMS)
1 10 100
1000
1
V
GS
= 0 V
Figure 10. Diode Forward Voltage vs. Current
100
0.6 0.7 1
5
10
15
t
r
t
d(off)
t
d(on)
t
f
10
V
DD
= 15 V
I
D
= 30 A
V
GS
= 11.5 V
0.8 0.9
20
30
25
T
J
= 25°C
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
V
GS
= 20 V
SINGLE PULSE
T
A
= 25°C
20
6
0
25
T
J
, JUNCTION TEMPERATURE (°C)
I
D
= 15 A
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
50 75 175
20
60
80
100 125
100
120
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
150
500
40
8
10
1
11
3
5
7
9
1 2 3 4 6 7 8 9 111213141516171819202122232425
Q
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
D
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
10 ms
1 ms
100 ms
10
0.01 10 100
1
1000
1
0.1
0.01
100
0.1
10 ms