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NOIS1SM0250A-HHC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
NOIS1SM0250A
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7
Figure 5 shows the increase in dark current under total dose irradiation. This curve is measured when the radiation is at high
dose rate. Annealing results in a significant dark current decrease.
Figure 5. Dark Current Increase
0
0,2
0,4
0,6
0,8
1
1,2
1,4
0
Total Ionizing Dos e [M r ad(Si)]
Dark current increase [nA/cm
2
]
2 4 6 8 10 12
Figure 6 shows the percentage of pixels with a dark current increase under 11.7 Mev radiation with protons.
Figure 6. Percentage of Pixels with Dark Current Increase
NOIS1SM0250A
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8
DC Operating Conditions
Table 5. DC SPECIFICATIONS
Symbol Parameter (Notes 1, 2 and 3) Min Typ Max Units
V
DD_ANA
Analog supply voltage to imager part – 5 – V
V
DD_DIG
Digital supply voltage to imager part – 5 – V
V
DD_ADC_ANA
Analog supply voltage to ADC – 5 – V
V
DD_ADC_DIG
Digital supply voltage to ADC – 5 – V
V
DD_ADC_DIG_3.3/5
Supply voltage of ADC output stage – 3.3 to 5 – V
V
IH
Logical ‘1’ input voltage 2.3 – V
DD
V
V
IL
Logical ‘0’ input voltage 0 – 1 V
V
OH
Logical ‘1’ output voltage 4.25 4.5 – V
V
OL
Logical ‘0’ output voltage – 0.1 1 V
V
DD_PIX
Pixel array power supply (default 5 V, the device is then
in ‘soft reset’. To avoid the image lag associated with
soft reset, reduce this voltage to 3–3.5 V ‘hard reset’)
– 5 – V
V
DD_RESL
Reset power supply – 5 – V
1. All parameters are characterized for DC conditions after establishing thermal equilibrium.
2. Unused inputs must always be tied to an appropriate logic level, for example, either VDD or GND.
3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. Take normal precautions to
avoid applying any voltages higher than the maximum rated voltages to this high impedance circuit.
NOIS1SM0250A
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9
SENSOR ARCHITECTURE
Y-Start Registeer-Decoder
9
10
D9...D0
Clk_ADC
Ain
Column Amplifiers
512
512
Ld_X
Rst
Sig
Progr. Gain
Amplifier
Blackref
Cal
G0
G1
Sync_YL
Clk_YL
Ld_Y
9
9
512
Y Address
Decoder / Shift Register
512
Rst
Sel
Col
Y Address
Decoder / Shift Register
10-bit ADC
Clk_YR
SyncYR
A8...A0
Aout
9
CLKX
Sync_X
X-Start Register
Figure 7. STAR250 Schematic
X Address
Decoder / Shift Register
R
S
Pixel Array
512 by 512 Pixels
The base line of the STAR250 sensor design consists of
an imager with a 512 by 512 array of active pixels at 25 mm
pitch. The detector contains on-chip correction for FPN in
the column amplifiers, a programmable gain output
amplifier, and a 10-bit ADC. Through additional preset
registers, the start position of a window can be programmed
to enable fast read out of only part of the detector array.
Pixel Structure
The image sensor consists of several building blocks as
outlined in Figure 7. The central element is a 512 by 512
pixel array with square pixels at 25 mm pitch. Unlike
classical designs, the pixels of this sensor contain four
photodiodes. This configuration enhances the MTF and
reduces the PRNU. Figure 8 shows an electrical diagram of
the pixel structure. The four photodiodes are connected in
parallel to the reset transistor (T1). Transistor T2 converts
the charge, collected on the photo diode node, to a voltage
signal that is connected to the column bus by T3. The reset
and read entrance of the pixel are connected to one of the Y
shift registers.
Figure 8. STAR250 Pixel Structure
T1
T2
T3
Read
Column Bus
Reset
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

NOIS1SM0250A-HHC

Mfr. #:
Buy NOIS1SM0250A-HHC
Manufacturer:
ON Semiconductor
Description:
IC IMAGE SENSOR STAR250 84JLCC
Lifecycle:
New from this manufacturer.
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