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RT8292ALGSP

P1-P3P4-P6P7-P9P10-P12P13-P14
RT8292A
10
DS8292A-04 October 2016www.richtek.com
©
Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
highest efficiency operation. However, it requires a large
inductor to achieve this goal.
For the ripple current selection, the value of ΔI
L
= 0.24(I
MAX
)
will be a reasonable starting point. The largest ripple
current occurs at the highest V
IN
. To guarantee that the
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
fI V





The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
Table 2. Suggested Inductors for Typical
Application Circuit
Component
Supplier
Series
Dimensions
(mm)
TDK VLF10045 10 x 9.7 x 4.5
TDK SLF12565 12.5 x 12.5 x 6.5
TAIYO
YUDEN
NR8040 8 x 8 x 4
OUT
IN
RMS OUT(MAX)
IN OUT
V
V
I = I 1
VV
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, one 10μF low ESR ceramic
capacitors are recommended. For the recommended
capacitor, please refer to table 3 for more detail.
The selection of C
OUT
is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for C
OUT
selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
C
IN
and C
OUT
Selection
The input capacitance, C
IN,
is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
OUT OUT
L
IN
VV
I = 1
fL V




Hiccup Mode
For the RT8292AH, Hiccup Mode Under Voltage Protection
(UVP) is provided. When the FB voltage drops below half
of the feedback reference voltage, V
FB
, the UVP function
will be triggered and the RT8292AH will shut down for a
period of time and then recover automatically. The Hiccup
Mode UVP can reduce input current in short-circuit
conditions.
Latch-Off Mode
For the RT8292AL, Latch-Off Mode Under Voltage
Protection (UVP) is provided. When the FB voltage drops
below half of the feedback reference voltage, V
FB
, UVP
will be triggered and the RT8292AL will shutdown in Latch-
Off Mode. In shutdown condition, the RT8292AL can be
reset via the EN pin or power input VIN.
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔI
L
increases with higher V
IN
and decreases with higher inductance.
Figure 4. The Resistors can be Selected to Set IC
Lockout Threshold
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
VIN
EN
GND
BOOT
FB
SW
7
5
2
3
1
L
R1
R2
V
OUT
V
IN
RT8292A
SS
8
C
SS
COMP
C
C
R
C
C
P
6
C
BOOT
C
OUT
C
IN
100k
8V
12V
R
EN2
R
EN1
10µF
4,
9 (Exposed Pad)
RT8292A
11
DS8292A-04 October 2016 www.richtek.com
©
Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
OUT L
OUT
1
VIESR
8fC




The output ripple will be highest at the maximum input
voltage since ΔI
L
increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
capacitors are all available in surface mount
packages.Special polymer capacitors offer very low ESR
value. However, it provides lower capacitance density than
other types. Although Tantalum capacitors have the highest
capacitance density, it is important to only use types that
pass the surge test for use in switching power supplies.
Aluminum electrolytic capacitors have significantly higher
ESR. However, it can be used in cost-sensitive applications
for ripple current rating and long term reliability
considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
response as described in a later section.
The output ripple, ΔV
OUT
, is determined by :
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR) and C
OUT
also begins to be charged
or discharged C
OUT
to generate a feedback error signal
for the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One way is by placing an
R-C snubber between SW and GND and locking them as
close as possible to the SW pin (see Figure 5). Another
method is by adding a resistor in series with the bootstrap
capacitor, C
BOOT
, but this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful on EMI performance. For detailed PCB layout
guide, please refer to the section Layout Considerations.
Figure 5. Reference Circuit with Snubber and Enable Timing Control
VIN
EN
GND
BOOT
FB
SW
7
5
2
3
1
L
10µH
100nF
22µFx2
R1
75k
R2
24k
V
OUT
3.3V/2A
10µF
Chip Enable
V
IN
4.5V to 23V
RT8292A
SS
8
C
SS
0.1µF
COMP
C
C
3.3nF
R
C
13k
C
P
NC
6
4,
9 (Exposed Pad)
C
BOOT
C
OUT
C
IN
R
BOOT
*
R
S
*
C
S
*
R
EN
*
C
EN
*
* : Optional
RT8292A
12
DS8292A-04 October 2016www.richtek.com
©
Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Figure 7. Derating Curves for RT8292A Package
(a) Copper Area = (2.3 x 2.3) mm
2
,
θ
JA
= 75°C/W
(b) Copper Area = 10mm
2
,
θ
JA
= 64°C/W
(c) Copper Area = 30mm
2
,
θ
JA
= 54°C/W
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum operation junction
temperature , T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8292A, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θ
JA
is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θ
JA
is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P
D(MAX)
= (125°C − 25°C) / (49°C/W) = 2.04W
(70mm
2
copper area PCB layout)
The thermal resistance θ
JA
of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θ
JA
can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6a), θ
JA
is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θ
JA
to 64°C/W. Even further,
increasing the copper area of pad to 70mm
2
(Figure 6.e)
reduces the θ
JA
to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8292A packages, the derating curves
in Figure 7 allow the designer to see the effect of rising
ambient temperature on the maximum power dissipation
allowed.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0 25 50 75 100 125
Ambient Temperature (°C)
Power Dissipation (W)
Copper Area
70mm
2
50mm
2
30mm
2
10mm
2
Min.Layout
Four Layer PCB
P1-P3P4-P6P7-P9P10-P12P13-P14

RT8292ALGSP

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