AD7533
Rev. C | Page 7 of 12
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
The simplified D/A circuit is shown in
Figure 7. An inverted
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the I
OUT
1 and I
OUT
2 bus lines,
thus maintaining a constant current in each ladder leg
independent of the switch state.
20kΩ
S1 S2 S3 SN
I
OUT
2
V
REF
I
OUT
1
R
FB
20kΩ 20kΩ 20kΩ
10kΩ
BIT 1 (MSB) BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
BIT 2 BIT 3
10kΩ 10kΩ
10kΩ
20kΩ
01134-001
Figure 7. Functional Diagram
One of the CMOS current switches is shown in Figure 8. The
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.
DTL/TTL/
CMOS
INPUT
+
13
2
TO LADDER
5
4
250Ω
7
6
89
I
OUT
1I
OUT
2
01134-007
Figure 8. CMOS Switch
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs high and digital
inputs low are shown in
Figure 9 and Figure 10. In Figure 9 with
all digital inputs low, the reference current is switched to I
OUT
2.
The current source I
LEAKAGE
is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the I
OUT
2 terminal. The off switch
capacitance is 35 pF, as shown on the I
OUT
1 terminal. Analysis of
the circuit for all digital inputs high, as shown in
Figure 10, is
similar to
Figure 9; however, the on switches are now on
Ter minal I
OUT
1. Therefore, there is the 100 pF at that terminal.
I
OUT
2
I
OUT
1
REF
I
REF
R
FB
I
LEAKAGE
R
01134-008
R
R 10kΩ
100pF
I
LEAKAGE
35pF
I/1024
Figure 9. Equivalent Circuit—All Digital Inputs Low
I
OUT
2
I
OUT
1
REF
I
REF
R
FB
I
LEAKAGE
R
01134-009
R
100pF
I
LEAKAGE
35pF
I/1024
R 10kΩ
Figure 10. Equivalent Circuit—All Digital Inputs High
