IRU1260CT Datasheet IRU1260CT | P4-P6

IRU1260

Rev. 1.9

07/03/01

APPLICATION INFORMATION

Introduction

The IRU1260 is a dual adjustable Low Dropout (LDO)

regulator packaged in a 7-pin TO-220 which can easily

be programmed with the addition of two external resis-

tors to any voltages within the range of 1.20 to 5.5V.

This voltage regulator is designed specifically for appli-

cations that require two separate regulators such as the

Intel Pentium II processors requiring 1.5V and 2.5V

supplies, eliminating the need for a second regulator

which results in lower overall system cost. When Vctrl

pin is connected to a supply which is at least 1V higher

than Vin, the dropout voltage improves by 30% which

makes it ideal for applications requiring less than the

standard 1.3V dropout given in the LDO products such

as IRU10XX series. The IRU1260 also provides an accu-

rate 1.20V voltage reference common to both regulators

for programming each output voltage. Other features of

the device include: fast response to sudden load current

changes, such as GTL+ termination application for

Pentium II family of microprocessors. The IRU1260 also

includes thermal shutdown protection to protect the de-

vice if an overload condition occurs.

Output Voltage Setting

The IRU1260 can be programmed to any voltages in the

range of 1.20V to 5.5V with the addition of R1 and R2

external resistors according to the following formula:

Figure 3 - Typical application of the IRU1260 for

programming the output voltage.

(Only one output is shown here)

The IRU1260 keeps a constant 1.20V between the Vfb

pin and ground pin. By placing a resistor R1 across these

two pins a constant current flows through R1, adding to

the IFB current and into the R2 resistor producing a volt-

age equal to the (1.2/R1)*R2 + IFB* R2 which will be

added to the 1.20V to set the output voltage as shown

in the above equation. Since the input bias current of the

amplifier (IFB) is only 0.02µA typically, it adds a very

small error to the output voltage and for most applica-

tions can be ignored. For example, in a typical 1.5V

GTL+application if R1=10.2KΩ and R2=2.55KΩ the er-

ror due to the Iadj is only 0.05mV which is less than

0.004% of the nominal set point. The effective input im-

pedance seen by the feedback pins (The parallel combi-

nation of R1 and R2) must always be higher than 1.8KΩ

in order for the regulator to start up properly.

Load Regulation

Since the IRU1260 does not provide a separate ground

pin for the reference voltage, it is not possible to provide

true remote sensing of the output voltage at the load.

Figure 4 shows that the best load regulation is achieved

when the bottom side of R1 resistor is connected di-

rectly to the ground pin of IRU1260 (preferably to the tab

of the device) and the top side of R2 resistor is con-

nected to the load. In fact, if R1 is connected to the load

side, the effective resistance between the regulator and

the load is gained up by the factor of (1+R2/R1), or the

effective resistance will be, Rp(eff)=Rp*(1+R2/R1). It is

important to note that for high current applications, this

can represent a significant percentage of the overall load

regulation and one must keep the path from the regula-

tor to the load as short as possible to minimize this

effect.

Figure 4 - Schematic showing connection for best load

regulation. (Only one output is shown here)

Vout

1260app2-1.0

Vin

Vctrl

Vref

IRU1260

Gnd

Vout

Vctrl

Vin

Vfb

1260app3-1.1

Vin

Vctrl

PARASITIC LINE

RESISTANCE

IRU1260

Gnd

Vout

Vctrl

Vin

Vfb

Where:

VREF = 1.20V Typically

IB = 0.02µA Typical

R1 and R2 as shown in Figure 3:

VOUT = VREF ×

o1 +

p + R2 × IB

IRU1260

Rev. 1.9

07/03/01

Stability

The IRU1260 requires the use of an output capacitor as

part of the frequency compensation in order to make the

regulator stable. Typical designs for the microprocessor

applications use standard electrolytic capacitors with

typical ESR in the range of 50 to 100mΩ and the output

capacitance of 500 to 1000µF. Fortunately as the ca-

pacitance increases, the ESR decreases resulting in a

fixed RC time constant. The IRU1260 takes advantage

of this phenomena in making the overall regulator loop

stable. For most applications a minimum of 100µF alu-

minum electrolytic capacitor with the maximum ESR of

0.3Ω such as Sanyo, MVGX series, Panasonic FA se-

ries as well as the Nichicon PL series insures both sta-

bility and good transient response. The IRU1260 also

requires a 1µF ceramic capacitor connected from Vin to

Vctrl and a 10Ω, 0.1W resistor in series with Vctrl pin in

order to further insure stability.

Thermal Design

The IRU1260 incorporates an internal thermal shutdown

that protects the device when the junction temperature

exceeds the maximum allowable junction temperature.

Although this device can operate with junction tempera-

tures in the range of 150$C, it is recommended that the

selected heat sink be chosen such that during maxi-

mum continuous load operation the junction tempera-

ture is kept below this number. Two examples are given

which shows the steps in selecting the proper regulator

heat sink for driving the Pentium II processor GTL+ ter-

mination resistors and the Clock IC using the IRU1260

in TO-220 or TO-263 packages.

Example # 1:

Assuming the following specifications:

The steps for selecting a proper heat sink to keep the

junction temperature below 135$C is given as:

1) Calculate the maximum power dissipation using:

2) Select a package from the data sheet and record its

junction to case (or Tab) thermal resistance.

Selecting TO-220 package gives us:

3) Assuming that the heat sink is black anodized, cal-

culate the maximum heat sink temperature allowed:

Assume , θSA = 0.05$C/W (heat-sink-to-case thermal

resistance for black anodized)

4) With the maximum heat sink temperature calculated

in the previous step, the heat-sink-to-air thermal re-

sistance θSA is calculated as follows:

5) Next, a heat sink with lower θ

SA than the one calcu-

lated in step 4 must be selected. One way to do this

is to simply look at the graphs of the “Heat Sink Temp

Rise Above the Ambient” vs. the “Power Dissipation”

and select a heat sink that results in lower tempera-

ture rise than the one calculated in previous step.

The following heat sinks from AAVID and Thermalloy

meet this criteria.

Air Flow (LFM)

0 100 200 300 400

Thermalloy 7021B 7020B 6021PB 7173D 7141D

AAVID 593101B 551002B 534202B 577102B 576802B

Note: For further information regarding the above com-

panies and their latest product offering and application

support contact your local representative or the num-

bers listed below:

Thermalloy...........PH# (214) 243-4321

AAVID.................PH# (603) 528-3400

VIN = 3.3V

VOUT2 = 1.5V

VOUT1 = 2.5V

IOUT2(MAX) = 5.4A

IOUT1(MAX) = 0.4A

TA = 35$C

θJC = 2.7$C/W

PD = IOUT1 × (VIN - VOUT1) + IOUT2 × (VIN - VOUT2)

PD = 0.4 × (3.3 - 2.5) + 5.4 × (3.3 - 1.5) = 10W

θSA = = = 7.24$C/W

∆T

72.4

∆T = TS - TA = 107.4 - 35 = 72.4$C

TS = TJ - PD × (θJC + θCS)

TS = 135 - 10 × (2.7 + 0.05) = 107.4$C

IRU1260

Rev. 1.9

07/03/01

Example # 2:

Assuming the following specifications:

The steps for selecting a proper heat sink to keep the

junction temperature below 135$C is given as:

1) Calculate the maximum power dissipation using:

2) Assuming a TO-263 surface mount package, the junc-

tion to ambient thermal resistance of the package is:

3) The maximum junction temperature of the device is

calculated using the equation below:

Since this is lower than our selected 135$C maxi-

mum junction temperature (150$C is the thermal shut-

down of the device), TO-263 package is a suitable

package for our application.

Layout Consideration

The IRU1260 like all other high speed linear regulators

need to be properly laid out to insure stable operation.

The most important component is the output capacitor,

which needs to be placed close to the output pin and

connected to this pin using a plane connection with a

low inductance path.

IRU1260 in Ultra LDO, Single Output Application

The IRU1260 can also be used in single supply applica-

tions where the difference between input and output is

much lower than the standard 1.5V dropout that is ob-

tainable with standard LDO devices. The schematic in

Figure 7 shows the application of the IRU1260 in a single

supply with the second LDO being disabled.

In this application, the IRU1260 is used on the VGA

card to convert 3.3V supply to 2.7V to power the Intel

740 chip rather than the conventional LDO which due to

its 1.5V minimum dropout spec must use the 5V supply

to achieve the same result. The difference is a substan-

tial decrease in the power dissipation as shown below.

The maximum power dissipation of the I740 chip is 5.8W,

which at 2.7V results in:

a) Using standard LDO, the power dissipated in the de-

vice is:

D = (Vin - Vo) × Io = (5 - 2.7) × 2.15 = 4.94W

Using surface mount TO-263 package with 25$C/W

junction to air thermal resistance results in:

TJ = PD × θJA + TA = 4.94 × 25 + 25 = 148$C

This is very close to the thermal shutdown of the IC.

b) Using IRU1260, the power dissipated in the device is

drastically reduced by using 3.3V supply instead of

5V.

PD = (Vin - Vo) × Io = (3.3 - 2.7) × 2.15 = 1.3W

Using surface mount TO-263 package with 25$C/W

junction to air thermal resistance results in:

TJ = PD × θJA + TA = 1.3 × 25 + 25 = 57$C

A reduction of 91$C in junction temperature.

VIN = 3.3V

VOUT2 = 1.5V

VOUT1 = 2.5V

IOUT2(MAX) = 1.4A

IOUT1(MAX) = 0.2A

TA = 35$C

PD = IOUT1 × (VIN - VOUT1) + IOUT2 × (VIN - VOUT2)

PD = 0.2 × (3.3 - 2.5) + 1.5 × (3.3 - 1.5) = 2.86W

θJA = 30$C/W for 1" square pad area

TJ = TA + PD × θJA

TJ = 35 - 2.86 × 30 = 121$C

Io = = 2.15A

5.8

2.7

P1-P3 P4-P6 P7-P9 P10-P10

IRU1260CT

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