72x
GND
INPUT
& V
ref
OUTPUT
& V
d
GND
3
4
1
2
Features
Lead-free Option Available
Operating Frequency: 0.1 GHz ~6.0 GHz
Noise Figure: 1.4 dB at 2 GHz
Gain: 14 dB at 2 GHz
Bypass Switch on Chip Loss = -2.5 dB (Id <5 µA)
IIP3 = +35 dBm
Adjustable Input IP3: +2 to +14 dBm
2.7 V to 4.2 V Operation
Very Small Surface Mount Package
Applications
CDMA (IS-95, J-STD-008) Receiver LNA Transmit
Driver Amp
TDMA (IS-136)Handsets
Surface Mount Package
SOT-343 (SC-70)
Description
Avagos MGA-72543 is an economical, easy-to-use GaAs
MMIC Low Noise Ampli er (LNA),which is designed for an
adaptive CDMA receiver LNA and adaptive CDMA transmit
driver ampli er.
The MGA-72543 features a minimum noise  gure of 1.4 dB
and 14 dB associated gain from a single stage, feedback
FET ampli er. The output is internally matched to 50Ω.
The input is optimally internally matched for lowest noise
gure into 50Ω. The input may be additionally externally
matched for low VSWR through the addition of a single
series inductor. When set into the bypass mode,both input
and output are internally matched to 50Ω.
The MGA-72543 o ers an integrated solution of LNA with
adjustable IIP
3
. The IIP
3
can be  xed to a desired current
level for the receiver’s linearity requirements. The LNA has
a bypass switch function,which sets the current to zero
and provides low insertion loss. The bypass mode also
boosts dynamic range when high level signal is being
received.
For the CDMA driver ampli er applications, the MGA-
72543 provides suitable gain and linearity to meet the
ACPR requirements when the handset transmits the
highest power. When transmitting lower power, the MGA-
72543 can be bypassed, saving the drawing current.
The MGA-72543 is a GaAs MMIC, processed on Avagos
cost e ective PHEMT (Pseudomorphic High Electron Mo-
bility Transistor). It is housed in the SOT343 (SC70 4-lead)
package, and is part of the Avago Technologies CDMAd-
vantage RF chipset.
Pin Connections and Package Marking
Package marking is 3 characters. The last
character represents date code.
Attention:
Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
MGA-72543
PHEMT* Low Noise Ampli er with Bypass Switch
Data Sheet
*Pseudomorphic High Electron Mobility Transistor
2
Simpli ed Schematic
MGA-72543 Absolute Maximum Ratings
[1]
Symbol Parameter Units Absolute Operation
Maximum Maximum
V
d
Maximum Input to Output Voltage V 5.5 4.2
V
ref
Maximum Input to Ground DC Voltage V +0.3 +0.1
-5.5 -4.2
I
d
Supply Current mA 70 60
P
d
Power Dissipation
[2,3]
mW 300 250
P
in
CW RF Input Power dBm +20 +13
T
j
Junction Temperature °C 170 150
T
STG
Storage Temperature °C -65 to +150 -40 to +85
Thermal Resistance:
[2]
jc
= 200°C/W
Notes:
1. Operation of this device in excess of any of these limits may cause permanent damage.
2. Tcase = 25°C.
Functional Block Diagram
GND
GND
Output
& V
d
Control
GainFET
Input
&
V
ref
RF OUT
SW & Bias Control
RF IN
3
MGA-72543 Electrical Speci cations
T
c
= +25°C, Z
o
= 50, I
d
= 20 mA, V
d
= 3V, unless noted.
Symbol Parameters and Test Conditions Units Min. Typ. Max.
Vc
[1,3]
f = 2.0 GHz V
d
= 3.0V (V
ds
= 2.5V) I
d
= 20 mA V 0.37 0.51 0.65 0.035
NF test
[1]
f = 2.0 GHz V
d
= 3.0V (= V
ds
+ Vc) I
d
= 20 mA dB 1.5 1.8 0.06
G
a
test
[1]
f = 2.0 GHz V
d
= 3.0V (= V
ds
+ Vc) I
d
= 20 mA dB 13.5 14.4 15.5 0.13
IIP
3
test
[1]
f = 2.04 GHz V
d
= 3.0V (= V
ds
+ Vc) I
d
= 20 mA dB 8.5 10.5 0.67
IL test
[1]
f = 2.0 GHz V
d
= 3.0V (V
ds
= 0V, V
c
= 3V) I
d
= 0.0 mA dB 2.5 3.5 0.01
Ig test
[1]
f = 2.0 GHz V
d
= 3.0V (V
ds
= 0V, V
c
= 3V) I
d
= 0.0 mA µA 2.0 2.0
NF
o
[2]
Minimum Noise Figure f = 1.0 GHz dB 1.35
As measured in Figure 2 Test Circuit f = 1.5 GHz 1.38
( opt computed from s-parameter and f = 2.0 GHz 1.42 0.04
noise parameter performance as f = 2.5 GHz 1.45
measured in a 50 impedance  xture) f = 4.0 GHz 1.54
f = 6.0 GHz 1.70
G
a
[2]
Associated Gain at Nfo f = 1.0 GHz dB 14.8
As measured in Figure 2 Test Circuit f = 1.5 GHz 14.2
( opt computed from s-parameter and f = 2.0 GHz 13.6 0.11
noise parameter performance as f = 2.5 GHz 13.0
measured in a 50 impedance  xture) f = 4.0 GHz 11.2
f = 6.0 GHz 9.2
P
1dB
[1]
Output Power at 1 dB Gain Compression I
d
= 0 mA dBm +15.3
As measured in Figure 1 Test Circuit. I
d
= 5 mA +3.2
Frequency = 2.04 GHz
I
d
= 10 mA +8.3
I
d
= 20 mA +11.2 0.52
I
d
= 40 mA +14.9
I
d
= 60 mA +17.1
IIP
3
[1]
Input Third Order Intercept Point I
d
= 0 mA dBm +35
As measured in Figure 1 Test Circuit
I
d
= 5 mA +3.5
Frequency = 2.04 GHz I
d
= 10 mA +6.2
I
d
= 20 mA +10.5 0.67
I
d
= 40 mA +12.1
I
d
= 60 mA +14.8
ACP Adjacent Channel Power Rejection,
f = 2 GHZ, o set = 1.25 MHz, Pout = 10 dBm I
d
= 30 mA dBc -55
(CDMA modulation scheme) I
d
= 40 mA -60
f = 800 MHz, o set = 900 KHz, Pout = 8 dBm I
d
= 20 mA -57
As measured in Figure 1 Test Circuit I
d
= 30 mA -60
RL
in
[1]
Input Return Loss as measured in Fig. 1 f = 2.0 GHz dB 10.2 0.22
RL
out
[1]
Output Return Loss as measured in Fig. 1 f = 2.0 GHz dB 19.5 1.1
ISOL
[1]
Isolation |S
12
|
2
as measured in Fig. 2 f = 2.0 GHz dB -23.2 0.16
Notes:
1. Standard Deviation and Typical Data as measured in the test circuit in Figure 1. Data based at least 500 part sample size and 3 wafer lots.
2. Typical data computed from s-parameter and noise parameter data measured in a 50É∂ system. Data based on 40 parts from 3 wafer lots.
3. Vc = -Vref test
Figure 1. MGA-72543 Production Test Circuit.
Figure 2. MGA-72543 Test Circuit for S, Noise, and Power Parameters Over
Frequency.
RF
Input
V
ref
50 pF
960 pF
2.7 nH
18 nH
1000 W
V
d
RF
Output
72x
2
1
4
3
56 pF
56 p F
RF
Input
Bias Tee
V
d
RF
Output
72x
V
ref
Bias
Tee
ICM Fixture

MGA-72543-TR2G

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
IC AMP CDMA 100MHZ-6GHZ SOT343
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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