AD766ANZ

AD766
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ESD SENSITIVITY
The AD766 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the
AD766 has been classified as a Category 1 Device.
Proper ESD precautions are strongly recommended to avoid functional damage or perfor-
mance degradation. Charges as high as 4000 volts readily accumulate on the human body and
test equipment, and discharge without detection. Unused devices must be stored in conduc-
tive foam or shunts, and the foam discharged to the destination socket before devices are
removed. For further information on ESD precaution, refer to Analog Devices’ ESD
Prevention Manual.
ABSOLUTE MAXIMUM RATINGS*
V
L
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 13.2 V
V
S
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 13.2 V
–V
L
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V
–V
S
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . .–0.3 V to V
L
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Short Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN DESIGNATIONS
Pin Function Description
1–V
S
Analog Negative Power Supply
2 DGND Digital Ground
3V
L
Logic Positive Power Supply
4 NC No Connection
5
CLK Clock Input
6 LE Latch Enable Input
7 DATA Serial Data Input
8–V
L
Logic Negative Power Supply
9V
OUT
Voltage Output
10 R
F
Feedback Resistor
11 SJ Summing Junction
12 AGND Analog Ground
13 I
OUT
Current Output
14 MSB ADJ MSB Adjustment Terminal
15 TRIM MSB Trimming Potentiometer Terminal
16 V
S
Analog Positive Power Supply
ORDERING GUIDE
Temperature Package
Model Range Option*
AD766JN 0°C to +70°C N-16
AD766AN –40°C to +85°C N-16
AD766SD/883B –55°C to +125°C D-16
*N = Plastic DIP; D = Ceramic DIP.
CONNECTION DIAGRAM
AD766J AD766A
Parameter Min Typ Max Min Typ Max Units
TEMPERATURE RANGE
Specified 0 +70 –40 +85 °C
Storage –60 +100 –60 +100 °C
NOTES
1
For A grade only, voltage outputs are guaranteed only if +V
S
7 V and –V
S
–7 V.
2
Specified using external op amp, see Figure 3 for more details.
3
Tested at full-scale input.
4
For A grade only, power supplies must be symmetric, i.e., V
S
= |–V
S
| and +V
L
= |–V
L
|. Each supply must independently meet this equality within ±5%.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.
Specifications subject to change without notice.
AD766–Definition of Specifications
–4–
REV. A
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics to the value of the fundamental input frequency. It is ex-
pressed in percent (%) or decibels (dB).
THD is a measure of the magnitude and distribution of integral
linearity error and differential linearity error. The distribution of
these errors may be different, depending on the amplitude of the
output signal. Therefore, to be most useful, THD should be
specified for both large and small signal amplitudes.
SETTLING TIME
Settling Time is the time required for the output to reach and
remain within a specified error band about its final value, mea-
sured from the digital input transition. It is the primary measure
of dynamic performance.
BIPOLAR ZERO ERROR
Bipolar Zero Error or midscale error is the deviation of the ac-
tual analog output from the ideal output (0 V) when the 2s
complement input code representing half scale (all 0s) is loaded
in the input register.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error is the measure of the variation in
analog value, normalized to full scale, associated with a 1 LSB
change in the digital input. Monotonic behavior requires that
the differential linearity error not exceed 1 LSB in the negative
direction.
MONOTONICITY
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
SIGNAL-TO-NOISE RATIO
SNR is defined as the ratio of the fundamental to the square
root of the sum of the squares for the values of all the nonfun-
damental, nonharmonic signals for a specified bandwidth. SNR
is tested at full-scale input. The AD766 specifies SNR for
20 kHz and 250 kHz bandwidths.
FUNCTIONAL DESCRIPTION
Serial input data is clocked into the AD766’s shift register by
the falling edge of
CLK. Data is presumed to be in twos
complement format with MSB (i.e., the sign bit) clocked in first.
The shift register converts the most recently clocked-in 16 bits
to a parallel word. The falling edge of the latch enable (LE) sig-
nal causes the most recent parallel word to be transferred to the
internal DAC input latch. See Figure 2 for detailed serial port
timing requirements.
The contents of the DAC input latch cause the 16-bit DAC to
generate a corresponding current. This ±1 mA current is avail-
able directly on the I
OUT
pin.
To use the internal op amp, connect I
OUT
(Pin 13) directly to
the summing junction pin, SJ (Pin 11) and connect the feedback
resistor pin, R
F
(Pin 10) to V
OUT
(Pin 9). Note that the internal
op amp is in the inverting configuration. Using the internal
3 k feedback resistor, this op amp will produce ±3 V outputs.
One advantage of external pins at each end of the feedback
resistor is that it allows the user to implement a single pole
active low-pass filter simply by adding a capacitor across these
pins (Pins 10 and 13). The circuit can best be understood
redrawn as shown in Figure 1.
Figure 1. Low-Pass Filter Using External Capacitor
The frequency response from this filter will be
V
OUT
(s)
I
OUT
=
R
F
R
F
C
s +1
where R
F
is 3 k (±20%).
Figure 2. AD766 Serial Input Timing
–5–
REV. A
The digital ground pin returns ground current from the digital
logic portions of the AD766 circuitry. This pin should be con-
nected to the digital common point in the system.
As illustrated in Figure 5, the analog and digital grounds should
be connected together at one point in the system.
Figure 5. Recommended Circuit Schematic
POWER SUPPLIES AND DECOUPLING
The AD766 has four power supply input pins. ±V
S
provide the
supply voltages to operate the linear portions of the DAC in-
cluding the voltage reference, output amplifier and control am-
plifier. The ±V
S
supplies are designed to operate from ±5 V to
±12 V.
The ±V
L
supplies operate the digital portions of the chip, in-
cluding the input shift register and the input latching circuitry.
The ±V
L
supplies are also designed to operate from ±5 V to
±12 V. To assure freedom from latch-up, –V
L
should never go
more negative than –V
S
.
Special restrictions on power supplies apply to extended tem-
perature range versions of the AD766 that do not apply to the
commercial AD766J. First, supplies must be symmetric. That is,
+V
S
= u–V
S
u and +V
L
= u–V
L
u. Each supply must independently
meet this equality within ±5%. Since we require that –V
S
–V
L
to guarantee latch-up immunity, this symmetry principle implies
that the positive analog supply must be greater than or equal to
the positive digital supply, i.e., V
S
–V
L
for extended-temper-
ature range parts. In other words, the digital supply range must
be inside the analog supply range. Second, the internal op amp’s
performance in generating voltage outputs is only guaranteed if
+V
S
7 V (and –V
S
–7 V, by the symmetry principle). These
constraints do not apply to the AD766J.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these ca-
pacitors be placed as close as possible to the package pins as
well as the common points. The logic supplies, ±V
L
, should be
decoupled to digital common; and the analog supplies, ±V
S
,
should be decoupled to analog common.
The use of four separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portions of
the system, thus contributing to the performance as tested.
However, four separate voltage supplies are not necessary for
good circuit performance. For example, Figure 6 illustrates a
For applications requiring broader bandwidths and/or even
lower noise than that afforded by the AD766’s internal op amp,
an external op amp can easily by used in its place. I
OUT
(Pin 13)
drives the negative (inverting) input terminal of the external op
amp, and its external voltage output is connected to the feed-
back resistor pin, R
F
(Pin 10). To insure that the AD766’s un-
used internal op amp remains in a closed-loop configuration,
V
OUT
(Pin 9) should be tied to the summing junction pin, SJ
(Pin 11).
As an example, Figure 3 shows the AD766 using the AD744 op
amp as an external current-to-voltage converter. In this invert-
ing configuration, the AD744 will provide the same ±3 V out-
put as the internal op amp would have. Other recommended
amplifiers include the AD845 and AD846. Note that a single
pole of low-pass filtering could also be attained with this circuit
simply by adding a capacitor in parallel with the feedback resis-
tor as just shown in Figure 1.
Figure 3. External Op Amp Connections
Residual DAC differential linearity error around midscale can
be externally trimmed out, improving THD beyond the
AD766’s guaranteed tested specifications. This error is most
significant with low-amplitude signals because the ratio of the
midscale linearity error to the signal amplitude is greatest in this
case, thereby increasing THD. The MSB adjust circuitry shown
in Figure 4 can be used for improving THD with low-level sig-
nals. Otherwise, the AD766 will operate to its specifications
with MSB ADJ (Pin 14) and TRIM (Pin 15) unconnected.
Figure 4. Optional MSB Adjustment Circuit
ANALOG CIRCUIT CONSIDERATIONS
GROUNDING RECOMMENDATIONS
The AD766 has two ground pins, designated AGND (analog
ground) and DGND (digital ground). The analog ground pin is
the “high-quality” ground reference point for the device. The
analog ground pin should be connected to the analog common
point in the system. The output load should also be connected
to that same point.
Analog Circuit Considerations–AD766

AD766ANZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-Bit Current Steering w/ V-Ref
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New from this manufacturer.
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