AD766SD/883B Datasheet AD766JNZ, AD766ANZ, AD766SD/883B | P7-P9

AD766

REV. A

–6–

system where only a single positive and a single negative supply

are available. In this case, the positive logic and positive analog

supplies may both be connected to the single positive supply.

The negative logic and negative analog supplies may both be

connected to the single negative supply. Performance would

benefit from a measure of isolation between the supplies intro-

duced by using simple low-pass filters in the individual power

supply leads.

Figure 6. Alternate Recommended Schematic

Figure 7. Power Dissipation vs. Clock Frequency

As with most linear circuits, changes in the power supplies will

affect the output of the DAC. Analog Devices recommends that

well regulated power supplies with less than 1% ripple be incor-

porated into the design of any system using these device.

MEASUREMENT OF TOTAL HARMONIC DISTORTION

The THD specification of a DSP DAC represents the amount

of undesirable signal produced during reconstruction of a digital

waveform. To account for the variety of operating conditions

Figure 8. Distortion Test Circuit

in signal processing applications, the DAC is tested at two

output frequencies and at three signal levels over the full oper-

ating temperature ranges.

A block diagram of the test setup is shown in Figure 8. In this

test setup, a digital data stream, representing a 0 dB, –20 dB or

–60 dB sine wave is sent to the device under test. The frequen-

cies used are 1037 Hz and 49.07 kHz. Input data is latched into

the AD766 at 500 kSPS. The AD766 under test produces an

analog output signal using the on-board op amp for 1 kHz and

an external op amp for 50 kHz.

The automatic test equipment digitizes the output test wave-

form, and then an FFT to 250 kHz is performed on the results

of the test. Based on the first 9 harmonics of the fundamental

1037 Hz and the first 3 harmonics of the 49.07 kHz output

waves, the total harmonic distortion of the device is calculated.

Neither a deglitcher nor an MSB trim is used during the THD

test.

The circuit design, layout and manufacturing techniques em-

ployed in the production of the AD766 result in excellent THD

performance. Figure 9 shows the typical unadjusted THD per-

formance of the AD766 for various amplitudes of 1 kHz and

50 kHz sine waves. As can be seen, the AD766 offers excellent

performance even at amplitudes as low as 60 dB. Figure 10

illustrates the typical THD versus frequency performance from

the internal amplifier for a filtered AD766 output. At frequen-

cies greater than approximately 30 kHz, depending on the low-

pass filter used, an improvement in THD of 3–4 dB over the

performance shown in the figure can be achieved. Figure 11

illustrates the consistent THD performance of the AD766

over temperature.

Figure 9. Typical Unadjusted THD

–7–

REV. A

Applications–AD766

Figure 10. Typical THD vs. Frequency

Figure 11. THD vs. Temperature

INTERFACING THE AD766 TO DIGITAL SIGNAL

PROCESSORS

The AD766 is specifically designed to easily interface to several

popular digital signal processors (DSP) without any additional

logic. Such an interface reduces the possibility of interface prob-

lems and improves system reliability by minimizing component

count.

AD766 TO ADSP-2101

The ADSP-2101 incorporates two complete serial ports which

can be directly interfaced to the AD766 as shown in Figure 12.

The SCLK, TFS and DT outputs of the ADSP-2101 are con-

nected directly to the

CLK, LE and DATA inputs of the

AD766, respectively. SCLK is internally generated and can be

programmed to operate from 94 Hz to 6.25 MHz. Data (DT) is

valid on the falling edge of SCLK. After 16 bits have been trans-

mitted, the falling edge of TFS updates the AD766’s data latch.

Using both serial ports of the ADSP-2101, two AD766’s can be

directly interfaced with no additional hardware.

AD766 TO TMS320C25

Figure 13 shows the zero-chip interface to the TMS320C25.

The interface to other TMS320C2X processors is similar. Note

that the C25 should be run in continuous mode. The C25’s

frame synch signal (FSX) will be asserted at the beginning of

each 16-bit word but will actually latch in the previous word.

Figure 12. AD766 to ADSP-2101/ADSP-2102/ ADSP-2105/

ADSP-2111

Figure 13. AD766 to TMS320C25

The CLKS, FSX and DX outputs of the TMS320C25 are con-

nected to the

CLK, LE and DATA inputs of the AD766, re-

spectively. Data (DX) is valid on the falling edge of CLKX. The

maximum serial clock rate of the TMS320C25 is 5 MHz.

AD766 TO DSP56000/56001

Figure 14 shows the zero-chip interface to the DSP56000/

56001. The SSI of the 56000/56001 allows serial clock rates up

to fosc/4. SCK, SC2 and STD can be directly connected to the

CLK, LE and DATA inputs of the AD766. The CRA control

software configurable to various divisions of the master clock

frequency. The data (STD) is valid on the falling edge of SCK.

Figure 14. AD766 to DSP56000/DSP56001

AD766

REV. A

–8–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C1385a–16–3/91

PRINTED IN U.S.A.

16-Pin Plastic DIP (N-16)

D-16

16-Lead Side Brazed Ceramic DIP

P1-P3 P4-P6 P7-P9

AD766SD/883B

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Manufacturer:

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Digital to Analog Converters - DAC 16-Bit Current Steering w/ V-Ref

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AD766SD/883B

AD766SD/883B

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