1. General description
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a
GTL−/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs.
2. Features
n Operates as a 2-bit GTL−/GTL/GTL+ sampling receiver or as an LVTTL to
GTL−/GTL/GTL+ driver
n 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
n GTL input and output 3.6 V tolerant
n V
ref
adjustable from 0.5 V to 0.5V
CC
n Partial power-down permitted
n Latch-up protection exceeds 500 mA per JESD78
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
n Package offered: TSSOP8 (MSOP8) and VSSOP8
3. Quick reference data
[1] All typical values are measured at V
CC
= 3.3 V and T
amb
=25°C.
GTL2012
2-bit LVTTL to GTL transceiver
Rev. 01 — 9 August 2007 Product data sheet
Table 1. Quick reference data
Recommended operating conditions; T
amb
=25
°
C
Symbol Parameter Conditions Min Typ
[1]
Max Unit
C
i
input capacitance control inputs; V
I
= 3.0 V or 0 V - 2 2.5 pF
C
io
input/output capacitance A port; V
O
= 3.0 V or 0 V - 4.6 6 pF
B port; V
O
=V
TT
or 0 V - 3.4 4.3 pF
GTL; V
ref
= 0.8 V; V
TT
= 1.2 V
t
PLH
LOW-to-HIGH propagation delay An to Bn; see Figure 4 - 2.8 5 ns
t
PHL
HIGH-to-LOW propagation delay An to Bn; see Figure 4 - 3.4 7 ns
t
PLH
LOW-to-HIGH propagation delay Bn to An; see Figure 5 - 5.2 8 ns
t
PHL
HIGH-to-LOW propagation delay Bn to An; see Figure 5 - 4.9 7 ns
