ADT7481
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13
Table 16. LIST OF REGISTERS (continued)
Read
Address
(Hex)
LockCommentPower-On DefaultMnemonic
Write
Address
(Hex)
19 19 Remote 2 THERM Limit 0101 0101 (0x55) (85°C) Bit 3 Conf Reg = 1 Yes
20 20 Local THERM Limit 0101 0101 (0x55) (85°C) Yes
21 21 THERM Hysteresis 0000 1010 (0x0A) (10°C) Yes
22 22 Consecutive ALERT 0000 0001 (0x01) Yes
23 N/A Status Register 2 0000 0000 (0x00) No
24 24 Configuration 2 Register 0000 0000 (0x00) Yes
30 N/A Remote 2 Temperature Value High Byte 0000 0000 (0x00) No
31 31 Remote 2 Temp High Limit High Byte 0101 0101 (0x55) (85°C) Yes
32 32 Remote 2 Temp Low Limit High Byte 0000 0000 (0x00) (0°C) Yes
33 N/A Remote 2 Temperature Value Low Byte 0000 0000 (0x00) No
34 34 Remote 2 Temperature Offset High Byte 0000 0000 (0x00) Yes
35 35 Remote 2 Temperature Offset Low Byte 0000 0000 (0x00) Yes
36 36 Remote 2 Temp High Limit Low Byte 0000 0000 (0x00) (0°C) Yes
37 37 Remote 2 Temp Low Limit Low Byte 0000 0000 (0x00) (0°C) Yes
39 39 Remote 2 THERM Limit 0101 0101 (0x55) (85°C) Yes
3D N/A Device ID 1000 0001 (0x81)
3E N/A Manufacturer ID 0100 0001 (0x41) N/A
1. Writing to Address 0F causes the ADT7481 to perform a single measurement. It is not a data register as such, and it does not matter what
data is written to it.
Serial Bus Interface
Control of the ADT7481 is achieved via the serial bus.
The ADT7481 is connected to this bus as a slave device
under the control of a master device.
The ADT7481 has an SMBus timeout feature. When this
is enabled, the SMBus will typically timeout after 25 ms of
no activity. However, this feature is not enabled by default.
Set Bit 7 (SCL timeout bit) of the consecutive alert register
(Address 0x22) to enable the SCL timeout. Set Bit 6 (SDA
timeout bit) of the consecutive alert register (Address 0x22)
to enable the SDA timeout.
The ADT7481 supports packet error checking (PEC) and
its use is optional. It is triggered by supplying the extra clock
for the PEC byte. The PEC byte is calculated using CRC−8.
The frame check sequence (FCS) conforms to CRC−8 by the
polynomial:
C(x) + x
8
) x
2
) x
1
) 1 (eq. 1)
Consult the SMBus 1.1 specification for more
information (www.smbus.org
).
Addressing the Device
In general, every SMBus device has a 7-bit device
address, except for some devices that have extended, 10-bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7481 is available with one device address, 0x4C
(1001 100b). An ADT7481−1 is also available. The only
difference between the ADT7481 and the ADT7481−1 is the
SMBus address. The ADT7481−1 has a fixed SMBus
address of 0x4B (1001 011b). The addresses mentioned in
this datasheet are 7-bit addresses. The R/W
bit needs to be
added to arrive at an 8-bit address. Other than the different
SMBus addresses, the ADT7481 and the ADT7481−1 are
functionally identical.
The serial bus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDATA) while the serial clock line (SCLK)
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus a R/W
bit,
which determines the direction of the data transfer, that is,
whether data will be written to, or read from, the slave
device. The peripheral with the address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known as
the acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W
bit is 0, the master writes to the slave
device. If the R/W
bit is 1, the master reads from the slave
device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a stop signal.
ADT7481
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14
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master will
pull the data line high during the tenth clock pulse to assert
a stop condition. In read mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as no acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, then high during the tenth clock pulse to assert a stop
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the case of the
ADT7481, write operations contain either one or two bytes,
while read operations contain one byte.
To write data to one of the device data registers or to read
data from it, the address pointer register must be set so that
the correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
This procedure is illustrated in Figure 15. The device
address is sent over the bus followed by R/W
set to 0 and
followed by two data bytes. The first data byte is the address
of the internal data register to be written to, which is stored
in the address pointer register. The second data byte is the
data to be written to the internal data register.
Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
SCLK
SDATA
00
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7481
START BY
MASTER
19
1
ACK. BY
ADT7481
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7481
STOP BY
MASTER
1
9
SCLK (CONTINUED)
SDATA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
R/W
Figure 16. Writing to the Address Pointer Register Only
1
SCLK
SDATA
00
1
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7481
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
19
ACK. BY
ADT7481
9
R/W
Figure 17. Reading Data from a Previously Selected Register
1
SCLK
SDATA
00
1
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7481
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADT7481
1
19
ACK. BY
ADT7481
9
R/W
ADT7481
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15
When reading data from a register there are two possible
scenarios:
1. If the address pointer register value of the
ADT7481 is unknown or not the desired value, it
is necessary to set it to the correct value before
data can be read from the desired data register.
This is done by performing a write to the
ADT7481 as before, but only the data byte
containing the register read address is sent, as data
is not to be written to the register. This is shown in
Figure 16.
A read operation is then performed consisting of
the serial bus address, R/W
bit set to 1, followed
by the data byte read from the data register (shown
in Figure 17).
2. If the address pointer register is already at the
desired address, data can be read from the
corresponding data register without first writing to
the address pointer register, and the bus transaction
shown in Figure 16 can be omitted.
NOTES:It is possible to read a data byte from a data register without
first writing to the address pointer register. However, if the
address pointer register is already at the correct value, it is
not possible to write data to a register without writing to the
address pointer register. This is because the first data byte
of a write is always written to the address pointer register.
Remember that some of the ADT7481 registers have
different addresses for read and write operations. The write
address of a register must be written to the address pointer
if data is to be written to that register, but it may not be
possible to read data from that address. The read address
of a register must be written to the address pointer before
data can be read from that register.
ALERT Output
Pin 8 can be configured as an ALERT output. The ALERT
output goes low whenever an out-of-limit measurement is
detected, or if the remote temperature sensor is open circuit.
It is an open-drain output and requires a pullup. Several
ALERT
outputs can be wire-OR’ed together, so that the
common line will go low if one or more of the ALERT
outputs goes low.
The ALERT
output can be used as an interrupt signal to a
processor, or it may be used as an SMBALERT
. Slave
devices on the SMBus cannot normally signal to the bus
master that they want to talk, but the SMBALERT
function
allows them to do so.
One or more ALERT
outputs can be connected to a
common SMBALERT
line connected to the master. When
the SMBALERT
line is pulled low by one of the devices, the
following procedure occurs as illustrated in Figure 18.
Figure 18. Use of SMBALERT
ALERT RESPONSE
ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
RDSTART ACK
DEVICE
ADDRESS
NO
ACK
STOP
MASTER RECEIVES SMBALERT
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address that must not be used as a
specific device address.
3. The device with a low ALERT
output responds to
the alert response address, and the master reads the
address from the responding device. An LSB of 1
is added because the device address is comprised
of seven bits. The address of the device is now
known and it can be interrogated in the usual way.
4. If more than one device has a low ALERT
output,
the one with the lowest device address will have
priority, in accordance with normal SMBus
arbitration.
5. Once the ADT7481 has responded to the alert
response address, it will reset its ALERT
output,
provided that the error condition that caused the
ALERT
no longer exists. If the SMBALERT line
remains low, the master sends the ARA again, and
so on until all devices with low ALERT
outputs
respond.
Masking the ALERT Output
The ALERT output can be masked for local, Remote 1,
Remote 2 or all three channels. This is done by setting the
appropriate mask bits in either the Configuration 1 register
(read address = 0x03, write address = 0x09) or in the
consecutive ALERT
register (address = 0x22)
To mask ALERTs due to local temperature, set Bit 5 of the
consecutive ALERT
register to 1. Default = 0.
To mask ALERT
s due to Remote 1 temperature, set Bit 1 of
the Configuration 1 register to 1. Default = 0.
To mask ALERT
s due to Remote 2 temperature, set Bit 0 of
the Configuration 1 register to 1. Default = 0.
To mask ALERT
s due to any channel, set Bit 7 of the
Configuration 1 register to 1. Default = 0.
Low Power Standby Mode
The ADT7481 can be put into low power standby mode
by setting Bit 6 (Mon/STBY bit) of the Configuration 1
register (Read Address 0x03, Write Address 0x09) to 1.
The ADT7481 operates normally when Bit 6 is 0. When
Bit 6 is 1, the ADC is inhibited, and any conversion in
progress is terminated without writing the result to the
corresponding value register.
The SMBus is still enabled in low power standby mode.
Power consumption in this standby mode is reduced to a
typical of 5 mA if there is no SMBus activity, or up to 30 mA
if there are clock and data signals on the bus.
When the device is in standby mode, it is still possible to
initiate a one-shot conversion of both channels by writing to
the one-shot register (Address 0x0F), after which the device
will return to standby. It does not matter what is written to
the one-shot register, all data written to it is ignored. It is also
possible to write new values to the limit register while in

ADT7481ARMZ-R7

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
SENSOR DIGITAL 0C-127C 10MSOP
Lifecycle:
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