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IS62LV256AL-20JLI

P1-P3P4-P6P7-P9P10-P12P13-P13
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. D
07/20/2015
IS65LV256AL
IS62LV256AL
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
D
OUT
D
IN
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(OverOperatingRange)
-20 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Unit
twc WriteCycleTime 20 — 45 — ns
tsce CEtoWriteEnd 14 — 35 — ns
taw AddressSetupTimetoWriteEnd 14 — 25 — ns
tha AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwe
(4)
WEPulseWidth 14 — 25 — ns
tsd DataSetuptoWriteEnd 13 — 20 — ns
thd DataHoldfromWriteEnd 0 — 0 — ns
thzwe
(2)
WELOWtoHigh-ZOutput — 8 — 20 ns
tlzwe
(2)
WEHIGHtoLow-ZOutput 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3.0Vand
outputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the Write.
4. TestedwithOEHIGH.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/20/2015
IS65LV256AL
IS62LV256AL
Notes:
1. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the Write.
2. I/OwillassumetheHigh-ZstateifOE
≥
VIh.
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
tWC
tSCE
tSA tHA
tPWE
tAW
tHZWE
tSD
tHD
tLZWE
ADDRESS
D
IN
CE
WE
D
OUT
WRITE CYCLE NO. 2 (CE Controlled)
(1,2)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47749
Rev. D
07/20/2015
IS65LV256AL
IS62LV256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit
VdrVddforDataRetention SeeDataRetentionWaveform 2.0 3.6 V
Idr DataRetentionCurrent Vdd=2.0V,CE ≥Vdd–0.2V Com. — — 15 µA
VIn ≥ Vdd – 0.2V, or VIn
≤
Vss + 0.2V
Ind. — — 20
Auto. — — 50
typ.
(1)
2
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — ns
Note:
1.TypicalValuesaremeasuredatVdd=3.3V,Ta = 25
o
Candnot100%tested.
DATA RETENTION WAVEFORM (CE Controlled)
VDD
CE ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
P1-P3P4-P6P7-P9P10-P12P13-P13

IS62LV256AL-20JLI

Mfr. #:
Buy IS62LV256AL-20JLI
Manufacturer:
ISSI
Description:
SRAM 256K (32K x 8) 20ns Async SRAM 3.3v
Lifecycle:
New from this manufacturer.
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