STK10C68-5C45M

March 2006 1 Document Control # ML0006 rev 0.2
STK10C68
STK10C68-M SMD#5962-93056
8K x 8 nvSRAM
QuantumTrap CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
25ns, 35ns, 45ns and 55ns Access Times
STORE to Nonvolatile Elements Initiated by
Hardware
RECALL to SRAM Initiated by Hardware or
Power Restore
Automatic STORE Timing
10mA Typical I
CC
at 200ns Cycle Time
Unlimited READ, WRITE and RECALL Cycles
1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Industrial/Commercial)
100-Year Data Retention (Industrial/Commer-
cial)
Commercial, Industrial and Military Tempera-
tures
28-Pin DIP, SOIC and LCC Packages
DESCRIPTION
The Simtek STK10C68 is a fast static RAM with a nonvol-
atile element incorporated in each static memory cell. The
SRAM can be read and written an unlimited number of
times, while independent nonvolatile data resides in
Non-
volatile Elements. Data may easily be transferred from
the
SRAM to the Nonvolatile Elements (the STORE oper-
ation), or from the Nonvolatile Elements to the SRAM
(the RECALL operation), using the NE pin. Transfers
from the Nonvolatile Elements to the
SRAM (the
RECALL operation) also take place automatically on
restoration of power.
The STK10C68 combines the high
performance and ease of use of a fast
SRAM with nonvol-
atile data integrity.
The STK10C68 features industry-standard pinout for non-
volatile RAMs. MIL-STD-883 and Standard Military Draw-
ing (SMD #5962-93056) devices are available.
BLOCK DIAGRAM
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
128 x 512
ROW DECODER
INPUT BUFFERS
QUANTUM TRAP
128 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
A
11
A
7
A
8
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
G
E
W
A
6
A
5
A
3
A
2
A
0
A
1
A
10
A
12
A
9
NE
A
4
PIN NAMES
A
0
- A
12
Address Inputs
W Write Enable
DQ
0
- DQ
7
Data In/Out
E Chip Enable
G Output Enable
NE Nonvolatile Enable
V
CC
Power (+ 5V)
V
SS
Ground
PIN CONFIGURATIONS
NE
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
NC
A
8
A
9
A
11
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - LCC
28 - DIP
28 - SOIC
STK10C68
March 2006 2 Document Control # ML0006 rev 0.2
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS (V
CC
= 5.0V ± 10%)
Note b: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
2
is the average current required for the duration of the STORE cycle (t
STORE
) .
Note d: EV
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCE
e
(T
A
= 25°C, f = 1.0MHz)
Note e: These parameters are guaranteed but not tested.
SYMBOL PARAMETER
COMMERCIAL
INDUSTRIAL/
MILITARY
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
b
Average V
CC
Current 85
75
65
N/A
90
75
65
55
mA
mA
mA
mA
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
I
CC
2
c
Average V
CC
Current during STORE 3 3 mA All Inputs Don’t Care, V
CC
= max
I
CC
3
b
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
SB
1
d
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
27
23
20
N/A
28
24
21
20
mA
mA
mA
mA
t
AVAV
= 25ns, E V
IH
t
AVAV
= 35ns, E V
IH
t
AVAV
= 45ns, E V
IH
t
AVAV
= 55ns, E V
IH
I
SB
2
d
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
750 1500 μA
E (V
CC
– 0.2V)
All Others V
IN
0.2V or (V
CC
– 0.2V)
I
ILK
Input Leakage Current
±1 ±1 μA
V
CC
= max
V
IN
= V
SS
to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 μA
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G V
IH
V
IH
Input Logic “1” Voltage 2.2 V
CC
+ .5 2.2 V
CC
+ .5 V All Inputs
V
IL
Input Logic “0” Voltage V
SS
– .5 0.8 V
SS
– .5 0.8 V All Inputs
V
OH
Note a: Output Logic “1” Voltage 2.4 2.4 V
I
OUT
= 4mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA
T
A
Operating Temperature 0 70 –40/-55 85/125 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance
8 pF
ΔV = 0 to 3V
C
OUT
Output Capacitance
7 pF
ΔV = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
STK10C68
March 2006 3 Document Control # ML0006 rev 0.2
SRAM READ CYCLES #1 & #2 (V
CC
= 5.0V ± 10%)
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < V
IL
, W > V
IH
, and NE V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
SRAM READ CYCLE #2: E Controlled
f
NO.
SYMBOLS
PARAMETER
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1 t
ELQV
t
ACS
Chip Enable Access Time 25 35 45 55 ns
2 t
AVAV
f
t
RC
Read Cycle Time 25 35 45 55 ns
3 t
AVQV
g
t
AA
Address Access Time 25 35 45 55 ns
4 t
GLQV
t
OE
Output Enable to Data Valid 10 15 20 25 ns
5 t
AXQX
g
t
OH
Output Hold after Address Change 5 5 5 5 ns
6 t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7 t
EHQZ
h
t
HZ
Chip Disable to Output Inactive 10 10 12 12 ns
8 t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9 t
GHQZ
h
t
OHZ
Output Disable to Output Inactive 10 10 12 12 ns
10 t
ELICCH
e
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
d, e
t
PS
Chip Disable to Power Standby 25 35 45 55 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ

STK10C68-5C45M

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 64K PARALLEL 28CDIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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